Encoding (memory)

About: Encoding (memory) is a research topic. Over the lifetime, 7547 publications have been published within this topic receiving 120214 citations. The topic is also known as: memory encoding & encoding of memories.

Positive reward prediction errors during decision-making strengthen memory encoding

Abstract: Dopamine is thought to provide reward prediction error signals to temporal lobe memory systems, but the role of these signals in episodic memory has not been fully characterized. Here we developed an incidental memory paradigm to (i) estimate the influence of reward prediction errors on the formation of episodic memories, (ii) dissociate this influence from surprise and uncertainty, (iii) characterize the role of temporal correspondence between prediction error and memoranda presentation and (iv) determine the extent to which this influence is dependent on memory consolidation. We found that people encoded incidental memoranda more strongly when they gambled for potential rewards. Moreover, the degree to which gambling strengthened encoding scaled with the reward prediction error experienced when memoranda were presented (and not before or after). This encoding enhancement was detectable within minutes and did not differ substantially after 24 h, indicating that it is not dependent on memory consolidation. These results suggest a computationally and temporally specific role for reward prediction error signalling in memory formation. Jang and colleagues show that positive reward prediction errors elicited during incidental encoding enhance the formation of episodic memories.

Systems and methods for securing media

Abstract: An apparatus for encoding videos having a central processing unit and a memory, coupled to the central processing unit, is provided. The memory has an Internet protocol (IP) address pool having IP addresses and a video encoding module. The video encoding module has instructions for obtaining a video source having a plurality of sequential frames. The video encoding module further has instructions for assigning select frames in the plurality of sequential frames with at least one IP address from the IP address pool, thereby forming an encoded video containing at least one embedded IP address. The video encoding module further has instructions for removing the at least one IP address from the IP address pool that is in the encoded video and instructions for storing the encoded video.

Video-information encoding method and video-information decoding method

Abstract: A video-information encoding apparatus and decoding apparatus with a guarantee of a fixed processing time. By limiting the amount of data to be input into/output from a CABAC encoding unit and decoding unit on a unit-of-encoding basis, such as one picture, slice, macroblock or block, and by encoding uncompressed video data, it is possible to provide a video-information encoding apparatus and decoding apparatus with a guarantee of a fixed processing time. Thereby, an apparatus with a guarantee of the processing time can be mounted.

Encoding image data for decode rate control

Abstract: One or more encoding parameters are controlled during the encoding of image data based on a decode processing rate. By taking decode processing into account during encoding, a decoding system will be able to keep up with the demands for decoding the resulting encoded bitstream. In one embodiment, encoding parameters used for video encoding may be changed iteratively to achieve a specified target decode processing rate, which can change from frame to frame.

Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system

Abstract: A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.