Showing papers on "Equivalent circuit published in 1984"

Quantum network theory

Abstract: A general approach, within the framework of canonical quantization, is described for analyzing the quantum behavior of complicated electronic circuits. This approach is capable of dealing with electrical networks having nonlinear or dissipative elements. The techniques are applied to circuits capable of generating squeezed-state or two-photon coherent-state signals. Circuits capable of performing back-action-evading electrical measurements are also discussed.

Switch-induced error voltage on a switched capacitor

Abstract: A concise analytical expression for switch-induced error voltage on a switched capacitor is derived from the distributed MOSFET model. The result can be interpreted in terms of a simple lumped equivalent circuit. With this expression the dependence is investigated of the error voltage on process parameters and on switch turnoff rate, source resistance, and other circuit parameters. These results can be used to quickly predict the error voltage. The analytical expression is in close agreement with computer simulations and experiments.

Relaxation-Based Electrical Simulation

Abstract: Circuit simulation programs have proven to be most important computer-aided design tools for the analysis of the electrical performance of integrated circuits. One of the most common analyses performed by circuit simulators and the most expensive in terms of computer time is nonlinear time-domain transient analysis. Conventional circuit simulators were designed initially for the cost-effective analysis of circuits containing a few hundred transistors or less. Because of the need to verify the performance of larger circuits, many users have successfully simulated circuits containing thousands of transistors despite the cost. Recently, a new class of algorithms has been applied to the electrical IC simulation problem. New simulators using these methods provide accurate waveform information with up to two orders of magnitude speed improvement for large circuits. These programs use relaxation methods for the solution of the set of ordinary differential equations, which describe the circuit under analysis, rather than the direct sparse-matrix methods on which standard circuit simulators are based. In this paper, the techniques used in relaxation-based electrical simulation are presented in a rigorous and unified framework, and the numerical properties of the various methods are explored. Both the advantages and the limitations of these techniques for the analysis of large IC's are described

Nonlinear programming without computation

Abstract: Using the Kuhn-Tucker conditions from mathematical programming theory, a canonical nonlinear programming circuit for simulating general nonlinear programming problems has been developed. This circuit is canonical in the sense that its topology remains unchanged and that it requires only a minimum number of 2-terminal nonlinear circuit elements. Rather than solving the problem by iteration using a digital computer, we obtain the answer by setting up the associated nonlinear programming circuit and measuring the node voltages. In other words, the nonlinear programming circuit is simply a special purpose analog computer containing a repertoire of nonlinear function building blocks. To demonstrate the feasibility and advantage of this approach, several circuits have been built and measured. In all cases, the answers are obtained almost instantaneously in real time and are accurate to within 3 percent of the exact answers.

Simplest chaotic nonautonomous circuit

Abstract: On donne un diagramme de bifurcation pour un circuit non autonome extremement simple. C'est une connexion en serie d'une resistance lineaire, d'un inducteur lineaire et d'une capacite lineaire a 2 segments commandee par une source de tension sinusoidale. Le diagramme ressemble aux diagrammes observes experimentalement et avec des resultats numeriques obtenus avec des modeles beaucoup plus compliques. On donne egalement une section de l'attractor chaotique

Self-Consistent GaAs FET Models for Amplifier Design and Device Diagnostics

Abstract: A procedure has been developed for producing accurate and unique small-signal equivalent circuit models for carrier-mounted GaAs FET's. The procedure utilizes zero drain-source bias S parmeter tests to determine accurate values of carrier parasitics, and dc measurements to evaluate the FET's gate, source, and drain resistances. Subsequent S-parameter measurements at full bias are then used to resolve the FET into an equivalent circuit model that has only 8 unknown elements out of a possible 16. A technique for evaluating the frequency range of accurate data is presented and the FET model shown is useful well above the maximum frequency of measurement. Examples of device diagnostics are presented for RCA flip-chip mounted GaAs FET's.

A Waveguide-Based Launcher to Sustain Long Plasma Columns through the Propagation of an Electromagnetic Surface Wave

Abstract: Long plasma columns of high electron densities, in many instances preferable to the positive column plasmas of dc discharges, can be sustained by means of an electromagnetic surface wave that propagates along the column at microwave frequencies. This paper presents a waveguide-based launcher (surfaguide) that can efficiently generate such plasma columns. It is a broadband device that can be operated with microwave powers of the order of kilowatts. The surfaguide is described and analyzed in terms of equivalent circuit theory. Guidelines for its design and operation are given.

Analysis of interconnection delay on very high-speed LSI/VLSI chips using an MIS microstrip line model

Abstract: Using an MIS (metal-insulator-semiconductor) microstrip-line model for interconnection and its equivalent circuit representation, on-chip interconnection delay in very high-speed LSI/VLSI's is analyzed in the time domain, changing interconnection geometry, substrate resistivity, and terminal conditions. The results show the following: 1) the "lumped capacitance" approximation is inapplicable for interconnections in very high-speed LSI/VLSI's (t pd of below 100-200 ps); 2) as compared to the semi-insulating substrate, the presence of the slow-wave mode and mode transition in the semiconducting substrates causes 1.5-2 times increase in the delay time and 2-10 times increase in the rise time; and 3) in order to realize propagation delay times of less than 100 ps per gate at LSI/VLSI levels, the effective signal source resistance of the gate should be less than 500 Ω so as to long interconnections.

Strip gratings at a dielectric interface and application of Babinet’s principle: erratum

Abstract: In this paper, we consider the transmission-line model used to calculate the transmittance of thin metallic strip gratings (at wavelengths longer than the grating period) to resolve a conflict of published expressions for the effect of a thick dielectric substrate on the equivalent circuit capacitance of capacitive gratings. By using rigorous diffraction theory we establish the correct expression and derive a modified form of Babinet’s principle for use with strip gratings on dielectric boundaries. It is found that the equivalent circuit capacitance of a strip grating on the boundary between media of refractive indices n1 and n2 is larger than its free-space value by a factor (n12+n22)/2. The result is applicable in general to the capacitive part of the equivalent circuit of grid reflectors, which are widely used at submillimeter wavelengths. A useful set of rigorously calculated transmission curves for strip gratings is presented, and these are used to establish the range of validity of the transmission-line model.

Analysis and Design of a Single-Resonator GaAs FET Oscillator with Noise Degeneration

Abstract: This paper presents an analysis of a low-noise dielectric resonator GaAs FET oscillator in a frequency-locked loop (FLL), which is used for FM noise degeneration. In this circuit, one resonator serves both as the frequency-determining element of the oscillator and as the dispersive element of the discriminator. The results of the analysis are used to generate design guidelines. These guidelines were followed in an experimental realization of an X-band circuit. The measured FM noise was--120 and--142 dBc/Hz at 10- and 100-kHz offset frequencies, respectively, and corresponded closely to predicted results.

Transverse Resonance Analysis of Finline Discontinuities

Abstract: A transverse resonance technique is used to compute the resonant frequencies of a finline resonator containing the discontinuity to be analyzed. From this, the parameters of the equivalent circuit of the discontinuity are evaluated as functions of frequency and geometry of the structure.

A better understanding of CMOS latch-up

Abstract: Both lumped-element two-transistor circuit model and two-dimensional finite-element analyses are used to study the latch-up phenomena in CMOS structures. The equivalent circuit model offers a simple view on latch-up, while 2-D modeling provides more physics and quantitative understanding of latch-up. A generalized criterion for p-n-p-n latch-up is derived based on the equivalent circuit. 2-D modeling confirms the latch-up triggering condition described by the criterion. Furthermore, 2-D simulation models the entire latch-up process, including the dynamic triggering stage, and determines the intrinsic steady-state I - V characteristics of p-n-p-n devices.

A unified decomposition approach for fault location in large analog circuits

Abstract: This paper deals with the problem of fault location in analog circuits The circuit under test is decomposed into subnetworks using nodes at which voltages have been measured We localize the faults to within the smallest possible subnetworks according to the final decomposition Then, further identification of the faulty elements inside the subnetworks is carried out The method is applicable to large-networks, linear or nonlinear It requires a limited-number of measurement nodes and its on-line computation requirements are minimal The method is based on checking the consistency of KCL in the decomposed circuit A measure of the effect of tolerances on the elements is introduced, and a number of examples are considered to illustrate the application of the method in both the linear and the nonlinear cases

Dual-Gate MESFET Mixers

Abstract: A theoretical and experimental investigation of dual-gate MESFET mixers is presented. Based on a detailed analysis of the different nonlinear modes of DGFET's, a computer-aided modeling procedure has been developed, which allowed to recognize and optimize critical circuit and bias conditions for high conversion gain and IF bandwidth. Theoretical results are in good agreement with experiments on a 12-GHz TV reception mixer with 8-dB conversion gain and 800-MHz bandwidth.

Problems in Precision Modeling of the MOS Transistor for Analog Applications

Abstract: This paper summarizes the inadequacies of present MOSFET models as applied to analog circuit design and, in some cases, proposes solutions Both efficient models suitable for CAD and more complex models are considered Problem areas discussed include poor modeling of the moderate inversion region, poor modeling of the surface potential in strong inversion, ambiguous use of "threshold" voltages and poor expressions for them, poor modeling of the drain small-signal conductance, very poor modeling of intrinsic small-signal capacitances, inadequate small-signal equivalent circuit topologies, and poor implementation of known correct ideas in some CAD programs, including the dependence of the effective mobility on the substrate potential, the modeling of thermal noise in the nonsaturation region, and the modeling of ion-implanted devices

Transient Analysis of a Stripline Having a Corner in Three-Dimensional Space

Abstract: The transient analysis of electromagnetic fields has shown its utility not only in clarifying the variation of the fields in time but also in gaining information on mechanisms by which the distributions of an electromagnetic field at the stationary state are bronght about. We have recently proposed a new numerical method for the transient analysis in three-dimensioual space by formulating the equivalent circuit based on Maxwell's equation by Bergeron's method. The resultant nodal equatiou is uniquely formulated in the equivalent circuit for both the electric field and the magnetic field. In this paper, we deal with the stripline which should be analyzed essentially in three-dimensionaf space because of its structure, The time variation of the electric and magnetic field of the stripline having a comer is analyzed and the remarkable changing of distribution of the field is presented as a parameter of time and of conditions imposed by the corner stucture.

A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection

Abstract: A procedure to derive gate level equivalent circuits for CMOS combinational logic circuits is given. The procedure leads to a model containing AND, OR and NOT gates. Specifically it does not require memory elements as does an earlier model and also uses fewer gates. It is shown that tests for classical stuck-at-0 and stuck-at-1 faults in the equivalent circuit can be used to detect line stuck-at, stuck-open and stuck-on faults in the modeled CMOS circuit.

High speed buffer circuit particularly suited for use in sample and hold circuits

Abstract: A buffer circuit includes a main buffer circuit section formed of a pair of complementary input side transistors the bases of which are connected together to an input, a dummy circuit section having the same circuit construction as the main buffer circuit section, and a feedback signal section compares the output from the dummy circuit section with a predetermined value to provide a feedback signal which is supplied to the dummy circuit section and the main buffer circuit section so as to make the output of the dummy circuit section equal to that predetermined value.

Improved Interfacing of Electrical Machine Models to Electromagnetic Transients Programs

Abstract: A new technique is presented for interfacing electrical machine models with electromagnetic transients programs. The machine models with their associated controls, loads or turbines can be assembled as subroutines by the user and interfaced to the electrical network or other machine models directly. The machine models employ the standard state variable equations and may use any integration technique for solution. The technique does not require a Thevenin equivalent circuit of the electrical network.

A Planar Quasi-Optical Subharmonically Pumped Mixer Characterized by Isotropic Conversion Loss

Abstract: By using a subharmonically pumped circuit in a quasi-optical planar mixer, we have found it possible to use an LO frequency of one-half the normaf value with little added circuit complexity. This circuit shows conversion loss as low as 8.6dB +- 2 dB at 14 GHz. Through the means of a newly defined quasi-optical mixer parameter called isotiopic conversion loss (L/sub iso/), we find that performance of the mixer system degrades less than 10 dB from an RF input of 14 GHz to 35 GHz, which is more than twice the designed RF frequency.

Broad-band guided-wave electrooptic modulators

Abstract: Lumped-element Mach-Zehnder interferometric modulators have been designed, fabricated in LiNbO 3 , tested and analyzed. These modulators had 3 dB bandwidths from 280 MHz to 2.75 GHz and V π 's from 1 V to 4 V, respectively. A simple RLC equivalent circuit is utilized to model the packaged modulator performance and results are compared with those measured using a swept-frequency technique. The model is seen to break down at the higher frequencies due to a frequency-dependent resistance and the electrode and parasitic inductances are seen to limit the overall modulator performance. The effects of varying the electrode capacitance, resistance, or inductance on modulator performance are demonstrated.

Prediction of error probabilities for integrated digital synchronizers

Abstract: Synchronization errors occur when asynchronous digital signals are received by clocked digital systems Digital synchronizers are designed to minimize the probability of such errors Empirical determination of error probabilities, as used in the past, is not a viable method for large-scale integrated circuit because it is cumbersome, interferes with the circuit performance, and does not account for tolerances of circuit parameters The authors describe a complete method for predicting synchronization-error probabilities using circuit simulation and theoretical analysis The analysis includes the efforts of random noise The simulation model readily takes into account tolerances of the circuit parameters The direct observability of all parameters of the model enhances the understanding of the synchronization process and the reliability of the predictions

Integrated circuit programmable cross-point connection technique

Abstract: A technique for programming connections of conductors that is particularly adapted to be implemented as part of an integrated circuit so that a number of connections internal of the circuit can be made from outside the circuit in order to customize it after fabrication. A specific arrangement of five switching transistors is particularly advantageous for each cross-point of two conductors to be connected together in one of many possible ways. The desired switching arrangement at each cross-point may be programmed by use of the same conductors being interconnected to carry control signals from outside the circuit to a memory associated with each cross-point switching circuit. While these memories are being programmed, each cross-point is temporarily forced to a desired state for communicating the control signals from outside the circuit to the memories.

Analysis of Interconnection Delay on Very High-Speed LSI/VLSI Chips Using an MIS Microstrip Line Model

Abstract: Using an MIS (metal-insulator-semiconductor) microstrip-Iine model for interconnection and its equivalent circuit representation, on-chip interconnection delay in very high-speed LSI/VLSI's is analyzed in the time domain, changing interconnection geometry, substrate resistivity, and terminal conditions. The results show the following 1) the "lumped capacitance" approximation is inapplicable for interconnections in very high-speed LSI/VLSI's ( t/sub pd/ of below 100-200 ps); 2) as compared to the semi-insulating substrate, the presence of the slow-wave mode and mode transition in the semiconducting substrates causes 1.5-2 times increase in the delay time and 2-10 times increase in the rise time and 3) in order to realize propagation delay times of less than 100 ps per gate at LSI/VLSI levels, the effective signal source resistance of the gate should be less than 500 Omega so as to long interconnections.

On the origin of the humidity-sensitive electrical properties of porous aluminium oxide (sensor application)

Abstract: Porous Al2O3 films exhibit interesting humidity-sensitive electrical properties. The authors have found that the conventional electrical equivalent circuit approach to interpret the properties of an Al2O3 humidity sensor is inadequate. This paper discusses the shortcomings of the model and proposes a theory based on physical adsorption phenomena, surface conduction mechanisms and the dielectric properties of the Al2O3 film. It is shown that the capacitance and resistance characteristics of the sensor derived by the theory agree with the experimental characteristics both in the nature of the variation and the frequency dependence.

Ad converting circuit

Abstract: PURPOSE: To constitute inexpensively an A/D converting circuit having a function of over range detection by applying logical operation to a digital output of an A/D converter having no over range detecting function so as to obtain an over range signal thereby using the A/D converter without over range detection function. CONSTITUTION: An overflow detection circuit 7 of AND circuit constitution detecting that the level of all output bits of each output bit of an A/D converter 5 are at high level and an underflow detection circuit 8 of AND circuit constitution detecting that they are all at low level are provided. Then outputs of both the detection circuits are ORed to generate an over range output from an over range output terminal 9, allowing to constitute the inexpensive circuit only with simple logical circuits only. COPYRIGHT: (C)1986,JPO&Japio

Nonlinearity correction circuit for bandgap reference

Abstract: A curvature correction circuit for generating an output current of the general form T ln T. When applied as a curvature correction circuit to bandgap references, the circuit precisely offsets the inherent parabolic non-linearity of such circuits.

Field effect transistor current source

Abstract: A field effect transistor circuit generates a reference current that can obtain a desired temperature coefficient. The circuit is self-compensatory with respect to process variations, in that a "slow" process will produce a higher than normal current, while a "fast" process will give a lower one. This results in a tight spread of slew-rate, gain, gain-bandwidth, etc. in opamps, comparators, and other linear circuits. A simple adjustment in the circuit allows the temperature coefficient to be made positive or negative if so desired. An illustrative circuit is shown for CMOS technology, but can be applied to other field effect technologies.

Method for simulating system operation of static and dynamic circuit devices

Abstract: In a circuit system simulation model which may comprise a combination of physical dynamic circuit devices to be modeled, of physical static circuit devices to be modeled, and of means for controlling at least the operating sequence of the physical devices, a method is provided for exercising the circuit devices which comprises segregating strobe input signals from nonstrobe input signals to be presented to each circuit device and preserving order of strobe input transitions relative to each other and to nonstrobe input transitions while ignoring the order of nonstrobe input transitions relative to one another when presenting a sequence of input patterns to each circuit device.

A wide-band technique for vector summation and RMS-DC conversion

Abstract: A circuit configuration is presented for wideband analog computation of both the vector-sum function and the RMS-DC conversion function. Design of the circuit is based on a systematic approach to translinear circuit synthesis. Errors due to finite transistor current gain are compensated by means of a novel technique. Measured performance results based on an experimental monolithic implementation in a standard bipolar process are presented. Bandwidths of 25 and 80 MHz are achieved for vector summation and RMS-DC conversion, respectively.