Showing papers on "Equivalent circuit published in 1991"

Retiming synchronous circuitry

Abstract: This paper describes a circuit transformation calledretiming in which registers are added at some points in a circuit and removed from others in such a way that the functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex setV is a collection of combinational logic elements and the edge setE is the set of interconnections, each of which may pass through zero or more registers. We give anO(?VźE?lg?V?) algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomial-time solvable. This result yields a polynomial-time optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a chacterization of optimal retiming based on an efficiently solvable mixed-integer linear-programming problem.

A three-step method for the de-embedding of high-frequency S-parameter measurements

Abstract: The authors propose a general method of deembedding S-parameter measurements of the device-under-test (DUT) for which typical parasitics associated with probe pads and interconnect-metal lines can be deembedded from the measurement. The DUT is the analog silicon bipolar junction transistor including the pad and interconnects. This method includes the subtraction of the parasitic shunt y-parameters of the on-wafer open calibration pattern as well as the subtraction of the parasitic series z-parameters on the on-wafer open circuit which are taken from measurements of the short and through circuits. It is demonstrated that the calculated power loss for the pad and interconnect parasitics can be comparable to the power consumption of the advanced bipolar transistor at high frequencies (>or=10 GHz). A knowledge of the magnitude and type of parasitic deembedding circuit elements can aid the device engineer in the analysis of the error associated with deembedding. >

On the power of small-depth threshold circuits

Abstract: We investigate the power of threshold circuits of small depth. In particular, we give functions that require exponential size unweighted threshold circuits of depth 3 when we restrict the bottom fanin. We also prove that there are monotone functionsf k that can be computed in depthk and linear size ⋎, ⋏-circuits but require exponential size to compute by a depthk−1 monotone weighted threshold circuit.

Technology Independent Large Signal Non Quasi-Static FET Models by Direct Construction from Automatically Characterized Device Data

Abstract: This paper describes a new, general and accurate, large signal GaAs FET model for nonlinear (e.g. harmonic balance) circuit simulation, its fast and unambiguous construction (model generation) by explicit calculations applied to the raw device data, and the adaptive, automated data acquisition system used to characterize the device. The model implementation in a harmonic balance simulator, the model generation procedure, and the automated data acquisition system form an efficient, practical, commercially available package. for state-of-the-art nonlinear circuit design.

High-frequency equivalent circuit of GaAs FETs for large-signal applications

Abstract: The application of GaAs field effect transistors in digital circuits requires a valid description by an equivalent circuit at all possible gate and drain bias voltages for all frequencies from DC up to the gigahertz range. An equivalent circuit is presented which takes into account the gate current of positively biased transistors as well as the symmetrical nature of the devices at low drain voltages. A fast method of determining the elements of the equivalent circuit at all bias points without frequency limitations is presented. Direct computation from analytical expressions, without iteration, allows this parameter extraction procedure to be used for real-time on-wafer parameter extraction. Large-signal calculations are possible by inserting the voltage dependences evaluation for the elements into suitable simulation programs, such as SPICE. >

RICE: Rapid interconnect circuit evaluator

Abstract: This paper describes RICE, an RLC interconnect evaluation tool based upon the moment-matching technique of Asymptotic Waveform Evaluation (AWE). The RLC circuit moments are calculated by a path-tracing algorithm which enables the analysis of large interconnect models several thousand times faster than a circuit simulation while requiring 5 to 10 times less memory. RICE also includes a new approach for determining the circuit dominant time-constants which avoids the inherent instability problems associated with moment matching methods in general.

Direct extraction of the AlGaAs/GaAs heterojunction bipolar transistor small-signal equivalent circuit

Abstract: The authors describe a novel, direct technique for determining the small-signal equivalent circuit of a heterojunction bipolar transistor (HBT). The parasitic elements are largely determined from measurements of test structures, reducing the number of elements determined from measurements of the transistor. The intrinsic circuit elements are evaluated from y-parameter data, which are DC-embedded from the known parasitics. The equivalent-circuit elements are uniquely determined at any frequency. The validity of this technique is confirmed by showing the frequency independence of the extracted circuit elements. The equivalent circuit models the HBT s-parameters over a wide range of collector currents. Throughout the entire 1-18-GHz frequency range, the computed s-parameters agree very well with the experimental data. >

Direct Extraction of the AlGaAs/GaAs Heterojunction Bipolar Transis tor Small- S ig nal Equivalent Circuit

Abstract: A technique for determining the small-signal equivalent-circuit model of an AIGaAs/GaAs heterojunction bipolar transistor (HBT) is presented. Most of the parasitic ele- ments are independently extracted from measurements of test structures. The intrinsic elements are calculated from y-parameter data, which are de-embedded from the previously determined parasitics. The agreement between the measured and model-produced data is excellent over the frequency range of 1 to 18 GHz. I. INTRODUCTION CCURATE, physically based equivalent circuits are A very useful for designing devices with reduced par- asitics and optimized performance. Although numerical optimization is often used to fit the model-generated s-parameters to the measured s-parameters, the resulting element values depend on the starting values and may be nonphysical. This uncertainty in the element values has been addressed by several authors. A new de-embedding method for determining the FET model was proposed by Dambrine et al. ( 11. Trew et al. (2) described a parameter extraction technique for an HBT that makes use of the emitter-to-collector time delay to constrain the element values used in optimization. We propose a new technique for determining the small-signal equivalent circuit of an HBT. With this technique, most of the parasitics are first obtained from measurements of test structures and those remaining are determined from measurements of the tran-

Impedance spectra of hydrating cement pastes

Abstract: Complex impedance spectra were obtained over the frequency range 5 Hz to 13 MHz on Portland cement pastes with water/cement ratios of 0.3, 0.35, and 0.4 at various hydration times from 6 h to 24 days. Features of the spectra which could be associated with the bulk material and which could be separated from the electrode arc, were studied. The overall bulk resistance of each paste was thereby determined as a function of hydration time. Bulk features evolved from a simple high-frequency intercept to an intercept with a single arc, then an intercept with two overlapping arcs, and back to an intercept with a single arc. A plausible equivalent circuit was developed involving an electrodeR/C network and constant phase element in series with one or two bulkR/C networks and a bulk resistor. Possible physical interpretation is discussed but assignment of equivalent circuit elements to microstructural features and/or processes will require microstructural characterization and a knowledge of pore-phase chemistry and properties.

A CMOS implementation of FitzHugh-Nagumo neuron model

Abstract: A CMOS circuit that emulates the FitzHugh-Nagumo neuron model is introduced. A complete derivation of the neuron model is presented, starting with the description of the fundamental biological mechanisms involved in the living neural cell, followed by the mathematical model formulation extracted from these mechanisms. A circuit theory technique for obtaining a physical IC suitable circuit that emulates the derived mathematical equations is then presented, culminating with the presentation of experimental results on a chip fabricated in a 2- mu m double-metal, double-poly CMOS process. It is emphasized that the FitzHugh-Nagumo model is very adequate for emulation of small biological systems. A reduced-complexity oscillatory model suitable for implementation of relatively large neural network architectures is also introduced with several corresponding CMOS realizations and measured results. >

Theoretical and experimental characterization of coplanar waveguide discontinuities for filter applications

Abstract: A full-wave analysis of shielded coplanar waveguide (CPW) two-port discontinuities based on the solution of an appropriate surface integral equation in the space domain is presented. Frequency-dependent scattering parameters for open-end and short-end CPW stubs are computed using this method. The numerically derived results are compared with measurements performed in the frequency range 5-25 GHz and show very good agreement. From the scattering parameters, lumped-element equivalent circuits have been derived to model the discontinuities. The inductors and capacitors of these models have been represented by closed-form equations, as functions of the stub length, to compute the circuit element values for these discontinuities. >

d-q ANALYSIS OF A VARIABLE SPEED DOUBLY AC EXCITED RELUCTANCE MOTOR

Abstract: The paper describes a new type of variable speed doubly-fed reluctance machine and presents the model for the analysis of the machine. The stator of the machine is equipped with two sets of sinusoidally distributed windings having pole numbers P1 and P2. The rotor consists of simple saliencies of pole number Pr, which is shown to be constrained to particular values by P1 and P2. A d-q-n model and equivalent circuit is developed for this machine. Simulation results using the new model show that this machine can have the advantages of doubly-fed wound-rotor machine while eliminating the complicated wound rotor, brushes and slip rings normally associated with doubly fed machines.

Equivalent-circuit parameter extraction for cold GaAs MESFET's

Abstract: The physical basis of the cold-FET method for extracting parasitic resistances and inductances is examined. A method to obtain the source resistance from the gate-current dependence of the FET Z parameters is used to analyze FETs with different gate lengths. Inductance results for FETs with different gate widths suggest that inductance extrinsic to the gate fingers is dominant, and models of the gate inductance support this. The effects that possible dependences of the parasitic-FET equivalent-circuit parameters (ECPs) on the gate and drain bias can have on the extracted intrinsic-FET parameters are discussed. >

Influence of supporting dielectric layers on the transmission properties of frequency selective surfaces

Abstract: Single layer arrays of linear dipole slots and patches symmetrically embedded in a dielectric layer or bonded to its surface illustrate dielectric tuning effects in this mainly computer aided but partly experimental study. After its initial rapid decline as the layer thickness increases, the resonant frequency of the slots varies cyclically about the limiting value for the patches. Contours of transmission level on a frequency/thickness plot illustrate this frequency pulling effect and lead to a discussion of passband shaping and the sensitivity to angle of incidence. Equivalent circuit concepts account for the observed bandwidth and resonant frequency variations. The performance of two experimental surfaces is described, including the influence of trapped waves in the dielectric.

A rigorous three plane mode-matching technique for characterizing waveguide T-junctions, and its application in multiplexer design

Abstract: A rigorous method for modeling rectangular waveguide T-junctions is presented. The method characterizes the waveguide discontinuity three times the side-arm of the T-junction is terminated in a short circuit with three different lengths, and hence is called the three plane mode-matching technique (TPMMT). Computed and measured data on both E-plane and H-plane T-junctions are compared, showing excellent agreement for the magnitudes and phases of the scattering matrix elements. Element values of equivalent circuit models are computed and approximated by simple polynomials or rational functions, given excellent accuracy. By using the S-parameters obtained from the TPMMT method, a network model of a waveguide manifold multiplexer is formulated. All parameters of the multiplexer, including the manifold dimensions and the filters, are optimized using this network model in terms of the multiplexer specification. The experimental results match the computed optimum results without further adjustment. >

Small signal equivalent circuit modeling of resonant converters

Abstract: A general analytical procedure is presented for the equivalent circuit modeling of resonant converters, using the series and parallel resonant converters as examples The switched tank elements of a resonant converter are modeled by a lumped parameter equivalent circuit The tank element circuit model consists, in general, of discrete energy states, but may be approximated by a low-frequency continuous time model These equivalent circuit models completely characterize the terminal behavior of the converters and are solvable for any transfer function or impedance of interest With the approximate model it is possible to predict the lumped parameter poles and zeros, and to quickly determine the relevant DC gains of the output impedance and the control to output transfer function Closed-form solutions are given for the equivalent circuit models of both converter examples Experimental verification is presented for the control-to-output transfer functions of both series and parallel resonant converters, and good agreement between theoretical prediction and experimental measurement is obtained >

Measurement-based system for modeling and simulation of active semiconductor devices over an extended operating frequency range

Abstract: A modeling system for active semiconductor devices, such as gallium arsenide field effect transistors, for nonlinear (e.g., harmonic balance) circuit simulation. The model enables fast and unambiguous construction (model generation) by explicit calculations applied to raw device response data obtained using an adaptive, automated data acquisition system employed to characterize the device. The automated data acquisition system obtains the data adaptively, taking more data where nonlinearities are most severe and within a calculated, safe operating range of the device. The system converts conventional d.c. and S-parameter data directly into a detailed, device-specific, large-signal model. The system is extremely fast and replaces the need for conventional parameter extraction based on circuit simulation and optimization techniques. The measurement-based model improves large-signal simulation accuracy over an extended operating frequency range, because the model nonlinearities are explicitly constructed from device response data. The model is non quasi-static in that it accounts for frequency dispersion effects. Scaling rules allow devices of various geometries to be simulated from measurements on a single device. Therefore, the model is general, being technology and process independent in that the same calculation procedure applies to any device for which the equivalent circuit is valid. The model implementation in the automated data acquisition system, model generator, and harmonic balance (nonlinear) circuit simulator provides an efficient, practical system for state-of-the-art nonlinear circuit design.

Transient state analysis of a doubly-fed induction generator under three phase short circuit

Abstract: The doubly fed induction generator (DFG) is a variable-speed constant-frequency generator operating in either subsynchronous or supersynchronous mode. The transient behavior of a symmetrically loaded DFG after a three-phase short circuit is presented. Both speed and rotor excitation voltage and frequency remain unchanged during short circuit. The complete mathematical model of the transient state and experimental results are given, along with the transient state equivalent circuit. >

Synthesis of averaged circuit models for switched power converters

Abstract: An approach for synthesizing averaged circuit models for switching converters that realize their respective state-space averaged models is presented. The method proceeds in a systematic fashion by determining appropriate averaged circuit elements that are consistent with the averaged circuit waveforms. The averaged circuit models that are obtained are syntheses of the state-space averaged models for the underlying switched circuits. An important feature of the method is that it is applicable to switched circuits whose non-switch elements may be nonlinear. This approach is compared and contrasted with the results on averaged circuit models available in the literature. >

Dynamic simulation of brushless doubly-fed machines

Abstract: Dynamic and steady-state models for the simulation of the performance of experimental brushless doubly-fed machines (BDFM) are presented. The dynamic simulation results are obtained using a two-axis representation which has been developed from a detailed machine design model. In turn, it is shown that several forms of steady-state equivalent circuit can be developed from the two-axis model for different specific modes of operation. Test data in dynamic conditions are compared with the predictions given by the two-axis model. It is concluded that these simplified models will provide adequate representation of full performance for control, stability, and scoping studies. >

A unified approach for the steady-state analysis of resonant converters

Abstract: A generalized approach for the steady-state analysis of resonant converters is presented. Different resonant converter tank circuit configurations are combined into a single tank circuit referred to as a generalized tank circuit. The load presented to this tank circuit is represented by an AC equivalent resistance, and simple complex circuit analysis is used to analyze such a generalized tank circuit. This type of unified approach simplifies the method of analysis for different configurations and eliminates the need for analysis of different schemes separately. In addition, in a computer program, the results for a particular scheme can be obtained by opening or shorting the nonrequired tank circuit components of the generalized scheme. The effect of high-frequency transformers and other parasitics can be taken into account in the analysis. A design example is presented to illustrate the method of designing a converter, and experimental results are presented to verify the analysis. >

Broadband monolithic passive baluns and monolithic double-balanced mixer

Abstract: The design and fabrication of four broadband monolithic passive baluns including CPW Marchand, multilayer MS Marchand, planar-transformer and broadside-coupled line baluns are presented. Operational frequencies range from 1.5 GHz to 24 GHz. Maximum relative bandwidths in excess of 3:1 are achieved. Simulated performances using full wave electromagnetic analysis are shown to agree with the measured results. Two accurate equivalent circuit models constructed from either electromagnetic simulated or measured S-parameters are developed for the MS Marchand and transformer baluns making the optimization of baluns and circuit design using the baluns much more efficient. The design of monolithic double-balanced diode mixer using two planar-transformer baluns is also presented. Without DC bias, the mixer shows a minimum conversion loss of 6 dB with the RF at 5 GHz and a LO drive of 15 dBm at 4 GHz. The measured input IP/sub 3/ of this mixer is better than 15 dBm over the 4 to 5.75 GHz frequency band. >

Impedance-matched, class F high-frequency amplifier

Abstract: An impedance matched class-F high frequency amplifier includes an input matching circuit receiving high frequency signals connected to the gate of the FET. The drain of the FET is connected to an output matching circuit which matches the fundamental frequency and the second harmonic frequency, and the output of the output matching circuit is connected to an even harmonic terminating circuit. The stray reactance componance at the output impedance of the FET is offset by the output matching circuit, and therefore the even harmonics terminating circuit can more accurately terminate the second harmonic frequencies.

Calculation of cage induction motor equivalent circuit parameters using finite elements

Abstract: A means by which the finite-element method can be used in conjunction with the conventional equivalent circuit model to determine the equivalent circuit components for a three-phase cage induction motor is described. The method uses separate finite-element models for the rotor and the stator, consisting of one slot pitch and one phase band, respectively. The use of minimal models leads to a fast execution time. The method is illustrated by comparing computer predictions of performance with test measurements made on four motors, ranging in size from 4 to 150 kW.

A switched reluctance motor model with mutual coupling and multi-phase excitation

Abstract: A novel switched reluctance motor (SRM) magnetic equivalent circuit model with mutual coupling and multiphase excitation is presented which successfully predicts the magnetic behavior of an SRM with multiple phase at a time excitation. The model is new in that it spreads the saturable elements throughout the machine rather than at the tooth tips. This allows the dominant mutual coupling effect, core saturation during multi-phase excitation, to be modeled. The authors describe methods for calculating or functionally representing values for the circuit elements given the machine geometry and a minimum number of finite-element models, a method for modeling saturable materials, and a method for solving the resulting mesh for flux values given excitation levels. The model results are compared with intermediate finite-element results. >

Semiconductor integrated circuit device comprising scan paths having individual controllable bypasses

Abstract: Three shift path circuits (10', 20', 30') each comprising a bypass circuit are connected in series between a test data input (TDI) and a test data output (TDO). Each shift path circuit constitutes a design definition test data register connected to a circuit to be tested. Design modification of a testing circuit can be minimized by selectively operating the bypass circuit provided in a shift path circuit, even if there is circuit modification in the circuit to be tested. The period of time required for testing circuits to be tested is reduced.

Bond programmable integrated circuit

Abstract: The described embodiments of the present invention provide a circuit and method for programming the mode options of an integrated circuit. The embodiment described provides this function for a dynamic random access memory but is applicable to any integrated circuit. The integrated circuit includes programming bonding pads which are either connected to a selected reference potential or left unconnected. Circuitry on the integrated circuit determines whether the pad is connected to the reference potential or is unconnected, and provides logical signals on the integrated circuit which select the operational mode of the integrated circuit. An additional feature of the described embodiment is a continuous checking to determine if the appropriate connected or unconnected state is being detected. This feature provides stray fields and other erroneous signals from altering the mode operation of the integrated circuit.

Insulated gate bipolar transistor (IGBT) modeling using IG-SPICE

Abstract: A physics-based model for the insulated gate bipolar transistor (IGBT) is implemented into the widely available circuit simulation package IG-SPICE. Based on analytical equations describing the semiconductor-physics, the model accurately describes the nonlinear junction capacitances, moving boundaries, recombination, and carrier scattering, and effectively predicts the device conductivity modulation. In this paper, the procedure used to incorporate the model into IG-SPICE and various methods necessary to ensure convergence are described. The effectiveness of the SPICE-based IGBT model is demonstrated by investigating the static and dynamic current sharing of paralleled IGBTs with different device model parameters. The simulation results are verified by comparison with experimental results. >

Lsi gate array having reduced switching noise

Abstract: As the number of output circuits in LSI or VLSI circuits increases, the chance of many large output circuits operating as a same instant increases, which can cause a malfunction in the logic due to induced switching noise. In order to prevent such a problem, the switching speed of the driving buffer circuit for an output buffer circuit is controlled. By reducing the switching capacity of the driving circuit, the switching speed of the total circuit is not greatly affected and the noise is greatly decreased. Control of the switching capacity of the driving buffer circuit is performed by master slice technology. This opposite design concept, compared to that of prior art LSI design, has been proved by experiments.