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Showing papers on "Equivalent series resistance published in 1981"


Journal ArticleDOI
TL;DR: In this article, a transparent conducting coating of Indium-Tin-Oxide (ITO) was applied over the existing metallic contact structure on solar cell front illuminated surface to reduce the sheet resistance of the diffused region.

85 citations


Journal ArticleDOI
TL;DR: In this article, a method is proposed which uses the observed nonlinearity in the short-circuit current versus light intensity curve at high intensities, to determine the series resistance of solar cells.
Abstract: A method is proposed which uses the observed nonlinearity in the short-circuit current versus light intensity curve at high intensities, to determine the series resistance of solar cells.

50 citations


Journal ArticleDOI
TL;DR: In this article, the magnetic field dependence of the transconductance of short-gate GaAs FET's was demonstrated to provide a direct means of characterizing the mobility profile of the active layer of the device, which does not require a capacitance measurement, and which is relatively insensitive to the parasitic series resistance associated with the source and drain contacts.
Abstract: It is demonstrated that the magnetic field dependence of the transconductance of short-gate GaAs FET's provides a direct means of characterizing the mobility profile of the active layer of the device, which does not require a capacitance measurement, and which is relatively insensitive to the parasitic series resistance associated with the source and drain contacts. The results are shown to be in agreement with those obtained from conventional measurements on a long-gate FET test structure.

43 citations


Journal ArticleDOI
TL;DR: In this paper, the authors derived analytical expressions for the photogenerated current and voltage of a solar cell, for the power at the maximum power point and for the curve factor of the solar cell.

35 citations


Journal ArticleDOI
TL;DR: In this article, a multilayer ceramic dieletric was used in binary system Pb(Fe 2/3 W l/3 )O 3 -Pb( Fe l/2 Nb l/ 2 )O3.
Abstract: Large capacitance multilayer ceramic capacitors were made using a ceramic dieletric in the binary system Pb(Fe 2/3 W l/3 )O 3 -Pb(Fe l/2 Nb l/2 )O3. The new capacitors used silver alloy as an internal electrode, reducing the capacitor cost significantly. It was then possible to make economical 10 µF ~ 400 µF muitilayer ceramic capacitors. Typical electrical properties of the new capacitors are listed below: Size 4.5 cm3Capacitance at 20° C, 1 kHz 400 µF Dissipation factor at 1 V rms, 1 kHz 0.6 percent Insulation resistance 5000 \Omega -F Capacitance change with temperature change (-30° C ~ +85° C) -83 to 0 percent Impedance at 100 kHz 2m \Omega 2 Equivalent series resistance at 100 kHz 0.8 m \Omega Maximum permissible ripple current 20 A. The new multilayer ceramic capacitors exhibit the following benefits in comparison with conventional multilayer ceramic capacitors, tantalum electrolytic capacitors, and aluminum electrolytic capacitors. a) Dimensions are small and capacitance is large; b) impedance at high frequency band is small; c) equivalent series resistance is small; d) maximum permissible ripple current is large. The new multilayer ceramic capacitors are useful in various electronic circuits, particularly in switching regulators, in place of tantalum electrolytic capacitors and aluminum electrolytic capacitors.

26 citations


Journal ArticleDOI
TL;DR: In this article, a tandem photovoltaic cell has been fabricated using a thin-film plastic electrolyte to connect in optical and electrical series an n-type CdS thinfilm and a p-type cdTe single crystal, with an open circuit voltage of 625 mV and a short-circuit current of 35 μA/cm2.
Abstract: A tandem photovoltaic cell has been fabricated using a thin‐film plastic electrolyte to connect in optical and electrical series an n‐type CdS thin‐film and a p‐type CdTe single crystal. The electrolyte was a thin film of poly(ethylene oxide) with a polysulfide redox couple. An open circuit voltage of 625 mV and a short‐circuit current of 35 μA/cm2 were obtained under illumination of 100 mW/cm2 with a xenon lamp. The cell output in the present configuration is limited by the series resistance and insufficient band bending in the semiconductor electrodes due to unfavorable resistance matching of the components.

25 citations


Proceedings ArticleDOI
01 Jan 1981
TL;DR: In this article, the performance of scaled n-channel and p-channel MOS devices is theoretically examined in detail down to 2 µm gate length including all of the major effects such as source/ drain series resistance, mobility degradation due to both parallel and perpendicular fields, and inversion layer capacitance under three different scaling schemes which are based on different power supply scenarios.
Abstract: The device performance of scaled n-channel and p-channel MOS devices is theoretically examined in detail down to 02 µm gate length including all of the major effects such as source/ drain series resistance, mobility degradation due to both parallel and perpendicular fields, and inversion layer capacitance under three different scaling schemes which are based on different power supply scenarios From the degradation factor of triode gain and drain saturation current, the relative contribution of each parasitic effect on device performance degradation has been examined Based on these calculations, some modifications to straightforward scaling are considered

18 citations


Proceedings ArticleDOI
01 Jan 1981
TL;DR: In this article, simulation is used to show how the lateral subdiffusion regions of S/D represent a dominant, V GS -dependent portion of the total resistance, since the doping profile there is steeply decreasing and the carrier concentration can be modulated by the gate voltage.
Abstract: At small V DS , g m reduction in MOSFET's is often attributed to mobility degradation due to increased vertical electric field with increasing V GS . This is correct for long channel devices; however, for short channel devices the parasitic series resistance of source/drain, R T , has a similar effect in reducing the g m value. In this paper, simulation is used to show how the lateral subdiffusion regions of S/D represent a dominant, V GS -dependent portion of the total resistance, since the doping profile there is steeply decreasing and the carrier concentration can be modulated by the gate voltage.

17 citations


Journal ArticleDOI
A.G. Steventon1, R. Spillett, R. Hobbs, M. Burt, P.J. Fiddyment, J. Collins 
TL;DR: In this article, a quantitative investigation of the constraints on dc operation of GaInAsP stripe-geometry lasers at room temperature and above has been made, and sets of theoretical curves have been generated that allow expected de thresholds to be determined from the value of the pulsed threshold.
Abstract: A quantitative investigation of the constraints on dc operation of GaInAsP stripe-geometry lasers at room temperature and above has been made. Laser pulse threshold current, its temperature sensitivity, electrical series resistance, and the thermal resistance of the bonded device are critical parameters in this respect. Sets of theoretical curves have been generated that allow expected de thresholds to be determined from the value of the pulsed threshold. Experimental results confirm the accuracy of the expressions. For GaInAsP lasers, the low values of T 0 reported in the literature (47-80 K) imply that both electrical series resistance and thermal resistance must be minimized in order to obtain stable dc operation over a reasonable temperature range in conventional oxide or proton isolated stripe structures. Both parameters are calculated theoretically for a range of structures. The calculations show that thermal runaway is sensitive to electrical resistance in the range 1-10 \Omega this suggests an area where improvements are possible. To this end, the use of tunneling Schottky contacts to a ternary InGaAs p-capping layer has been developed to minimize contact resistance.

14 citations


Patent
18 Mar 1981
TL;DR: In this article, the authors proposed a method to reduce a series resistance between source and drain without causing reduction of withstand voltage by a method wherein a low resistance layer having an impurity density higher than a drain layer at the channel side immediately under a gate electrode and through which carrier passes, is provided adjacent to a drain electrode.
Abstract: PURPOSE:To reduce a series resistance between source and drain without causing reduction of withstand voltage by a method wherein a low resistance layer having an impurity density higher than a drain layer at the channel side immediately under a gate electrode and through which carrier passes, is provided adjacent to a drain electrode. CONSTITUTION:N3 layer 22 and N2 layer (N2 Si substrate 1 and doubly diffused to form a base 3 and gate 4 and a gate oxide film 5, electrodes 6G, 6S and 6D are provided thereon further to form a GFET. The N3 layer 22 may be formed to increase its density increasingly to the substrate side. According to such a constitution, the resistance component for an area C having an intrinsic resistance Pn, thickness Tn and area A of the current paths from the source to the drain region is expressed by rhon.tn/A and the resistance in the area C can be reduced without reducing a withstand voltage through the provision of N3 layer 23 of high density. However, the area A and B have a great proportion to the total area and when they are reduced, the withstand voltage is reduced. However, is the high density layer 22 is provided so that the region C is permitted to have a low resistance, the IGFET with a high withstand voltage and a low rising resistance in static character can be obtained regardless of influence from withstand voltgae reduction.

13 citations


Journal ArticleDOI
TL;DR: In this paper, a low barrier (≲0.4 eV) microwave mixer diodes were fabricated by means of silicon molecular beam epitaxy (Si MBE) using a thin highly doped epitaxial layer to modify the electric field near the surface.
Abstract: Low barrier (≲0.4 eV) microwave mixer diodes were fabricated by means of silicon molecular beam epitaxy (Si MBE). Schottky barrier lowering was achieved by using a thin highly doped epitaxial layer to modify the electric field near the surface. The advantages of silicon MBE for these devices arise from the ability to grow epitaxial layers which are very precisely controlled in thickness and in the spatial distribution of dopant. The resulting diodes have both a low barrier height and a very low forward series resistance.

Journal ArticleDOI
TL;DR: In this article, the effective series resistance of a solar cell can be measured easily and accurately by the following simple technique: two successive pulses of equal intensity from a high intensity flashlamp are used to measure first open-circuit voltage V oc and secondly the voltage V L across a small known series load resistance R L.

Journal ArticleDOI
TL;DR: In this paper, a distributed model of an AlGaAs/GaAs solar cell is coupled to a ray trace model of a curved groove fresnel lens to predict cell performance under sunlight concentrated by such a lens.
Abstract: A distributed model of an AlGaAs/GaAs solar cell is coupled to a ray trace model of a curved groove fresnel lens to predict cell performance under sunlight concentrated by such a lens. The values of the equivalent circuit elements in the model are obtained experimentally by a novel flash test technique. Predictions compare closely to experiment, and it is found that contact grid series resistance plays an important role in performance.

01 Jun 1981
TL;DR: In this paper, the delta f technique was used to measure the series resistance, capacitance, and the Q factor of a coaxial transmission line with a test capacitor connected either in series at the shorted end of the line, or in shunt at the open end.
Abstract: A resonant coaxial transmission line, short circuited at one end and open circuited at the other, whose fundamental resonant frequency and Q factor are known, is perturbed with a test capacitor connected either in series at the shorted end of the line, or in shunt at the open end. Measuring the Q factor of the system with the delta f technique yields the effective series resistance, capacitance, and the Q factor of the test specimen. This method of measurement has the advantage that there are no adjustable elements to alter circuit conditions in an unprescribed way, the only variable is the frequency which can be measured with an uncertainty of less than 1 ppm, the loss of the line as a function of frequency is quite predictable, and the Q factor of the line can be made sufficiently high to support accurate measurements of low loss capacitors.

Journal ArticleDOI
TL;DR: These studies reveal changes in the absolute values and kinetics of the ionic currents (errors greater than 10-20%) for selected values of series resistance.

Journal ArticleDOI
TL;DR: In this article, an a.c. admittance method for axial and planar n -GaAs Schottky-barrier diodes is proposed. But the method is not suitable for the case of large leakage currents, large series resistance, at low forward voltages or near diode breakdown.
Abstract: As an extension of conventional CV measurements used for shallow impurity profiling an a.c. admittance method is described. By measuring the d.c.-voltage and frequency dependent conductance and susceptance components of axial and planar Schottky-barrier diodes the elements of the electrically equivalent circuits of these devices can be determined exactly. It is shown that within a frequency range of 0.11 MHz to about 500 MHz the diode admittance can be described by a discrete 3-element circuit consistint of a series resistance R s , a parallel resistance R p and a space-charge capacitance C . Knowing R s , R p and C it is possible to determine the exact CV d -dependence where V d is the d.c.-bias across the “inner” space charge. In consequence the applicability of this method is extended to cases where conventional bridge-based methods fail due to large leakage currents, large series resistance, at low forward voltages or near diode breakdown. The accuracy and limits of the proposed a.c. admittance method are discussed and typical experimental results on axial and planar n -GaAs Schottky-barrier diodes are presented.

Journal ArticleDOI
TL;DR: In this article, the influence of the illumination profile shape on the performance of concentrator silicon solar cells is shown through the variation of the series resistance under different illumination conditions, and the effect of the profile shape is investigated.
Abstract: The influence of the illumination profile shape on the performance of concentrator silicon solar cells is shown through the variation of the series resistance under different illumination conditions.

Proceedings ArticleDOI
01 Sep 1981
TL;DR: In this paper, coplanar Mott diodes with series resistance of about 4? with a total capacitance of.05 pF have been evaluated in 85 GHz balanced mixers.
Abstract: Conversion losses of 5.0 dB have been achieved at 35 GHz, with SSB noise figures of 6 dB (including 1 dB IF) using coplanar Mott diodes in finline balanced mixers. [l] The variation of noise figure with local oscillator power is significantly less than for conventional Schottky diodes, and results from the voltage independence of the capacitance of Mott diodes [2]. The series resistance of these diodes is about 4?, with a total capacitance of .05 pF. Smaller diodes, with capacitances of .03 pF, have been evaluated in 85 GHz balanced mixers. Conversion losses as low as 6.5 dB have been observed at 85 GHz, with improved operation over a wide range of local oscillator power, and further improvements are expected as devices and circuits are optimised at this frequency. In addition to achieving high performance the coplanar Mott diodes are made by low cost planar processing and are rugged.

Patent
10 Mar 1981
TL;DR: In this paper, a recess structure is formed in such a manner that the source side will have forward taper form and the drain side would have inverted taper forms. And the desired recessed structure was formed using the etchant which is the mixture of phosphoric acid and hydrogen peroxide, and then a dry etching was performed on the wafer.
Abstract: PURPOSE:To enable to sufficiently reduce the series resistance between gate and source and the capacitance between gate and source by a method wherein a recess structure is formed in such a manner that the source side will have forward taper form and the drain side will have inverted taper form. CONSTITUTION:An aperture is provided on the expected region 7 of a GaAs wafer 5 where a gate electrode will be formed using photoresist 6. Then, a dry etching is performed on the wafer 5. At this time, the wafer is inclinably positioned so that the GaAs etching makes progress with a tapered angle. Besides, the etching is performed using the etchant which is the mixture of phosphoric acid and hydrogen peroxide, and the desired recessed structure is formed. Subsequently, Al 8 is coated on the whole surface as a gate metal, and a gate 9 is formed by removing unnecessary metal. Then, a drain electrode 10 is formed on the inverted taper side and a source electrode 11 is formed on the forward taper side respectively. The GaAs FET manufactured as above has sufficiently small gate-source series resistance and gate-drain capacitance, thereby enabling to obtain excellent high frequency characteristics.

Journal ArticleDOI
TL;DR: In this paper, the specific contact resistance on epitaxially grown layers of p-In1−xGaxAsyP1−y as a function of composition is measured.
Abstract: Measurements of the specific contact resistance on epitaxially grown layers of p-In1−xGaxAsyP1−y as a function of composition demonstrate the resistance minimum of 7×10−6 Ωcm2 for In0.53Ga0.47As. Growth procedures for the preparation of InGaAsP/InP double-heterostructure LED wafers incorporating such a ternary InGaAs contact layer are described. This contacting technique allows fabrication of high-performance devices with reproducibly low series resistance.

Journal ArticleDOI
TL;DR: In this paper, the output performance of the coaxial-type Marx generator consisting of BaTiO3 series ceramic capacitors was theoretically analyzed, and the results were compared with experimental results, and fairly good agreement was obtained.
Abstract: We have theoretically analyzed the output performance of the coaxial‐type Marx generator consisting of BaTiO3 series ceramic capacitors. In this analysis, the capacitance of the BaTiO3 series ceramic capacitor has been considered to be variable with applied voltage. The results were compared with experimental results, and fairly good agreement was obtained. As a result of this analysis, it was clarified that the BaTiO3 series ceramic capacitor was not able to store efficiently the electrical energy when charged at high voltages. On the other hand, the SrTiO3 series ceramic capacitor has an almost constant capacitance against applied voltages, so that stored energy may be extracted efficiently. We have quantitatively revealed the superiority of SrTiO3 series ceramic capacitors over BaTiO3 series capacitors.

Journal ArticleDOI
L. Feinstein1, R. Pagano
TL;DR: In this article, a thin-film Ta capacitors with an Al underlay was used for high-frequency applications and the dissipation factor was found to be 0.0026 and 0.005 for the 700 and 3300 pF capacitors respectively.
Abstract: The use of thin-film Ta capacitors for precision applications is limited to frequencies below 10 KHz, due to the resistance of the Ta anode. The dissipation factor, Or tan \delta , in a resistancecapacitance (RC) series network is given by tan \delta =tan \delta ' + \omeg CR2, where tan \delta ' is an intrinsic loss due tO the dielectric, independent of frequency \omeg , and R 2 is the series resistance of electrodes and leads. By depositing the Ta on top of an Al film, which has a much lower resistivity than the Ta, the series resistance and therefore tan \delta Can be reduced, and the useful frequency range can be extended into the 1-MHz region. The processing, electrical properties, and life test characteristics are reported for a thin-film RC test circuit, with an Al underlay for high-frequency applications. In the process sequence selected, 0.25-1.0 µm of Al was deposited by evaporation or magnetically enhanced sputtering. Nitrogen doped body-centered cubic (bcc) Ta was then deposited by dc diode or magnetically enhanced sputtering, and the capacitors were patterned and anodized to 190V. Tantalum nitride resistors, a Ti-Pd-Au counterelectrode, and a 350°C 1-h stabilization completed the test circuits. Processing studies focused on the identification and elimination of problems associated with Al nodules (evaporation only), the adhesion of Al to a Ta 2 05 underlay, Al hillocks, resistance at the Al-Ta interface, and etching and undercutting. Values of tan \delta below o.oo2 were recorded from 1-100 KHz for 700- and 3300-pF capacitors with an Al underlay. At 1 MHz the dissipation factors were 0.0026 and 0.005 for the 700 and 3300 pF capacitors, respectively, compared with a value of 0.07 for 3300-pF controls without the underlay. Calculations Showed that the series resistance was reduced by a factor of 20 with the incorporation of an Al underlay. Electrical properties other than tan \delta were found to be unaffected by the presence of Al.

Patent
15 Dec 1981
TL;DR: In this paper, the authors proposed to enhance the accuracy of the divided voltage of respective output stages in a series resistance circuit network by obtaining accurate resistors even with low resistance value by preventing the error of the resistance value caused by the contacting part.
Abstract: PURPOSE:To enhance the accuracy of the divided voltage of respective output stages in a series resistance circuit network of two or more diffused resistors by obtaining accurate resistors even with low resistance value by preventing the error of the resistance value caused by the contacting part. CONSTITUTION:P type diffused resistance regions 9, 9' are formed in an N type region on a P type silicon substrate, and a series circuit of a resistor R1 and a resistor R2 is formed with diffused resistors formed at the junction of a P type contacting region 8 and a main electrode 7. When the resistance value of the R2 is less than 1/10 of the resistance value of the R1, the resistor R2 is formed by the parallel connection of many (four in this example) diffused resistors so as to obtain desired resistance value. That is, the resistance value R2 is obtained by the diffused resistor 9' having the length similar to or approximate to the diffused resistor 9 forming the R1. Thus, the effective length of the resistance can be increased, the ratio of the error caused by the contacting part can be reduced, and the absolute value of the low resistance can be accurately obtained.


Proceedings ArticleDOI
05 Apr 1981
TL;DR: In this paper, anodic oxidation thinning of GaAs epitaxial layers was used to optimize GaAs Schottky-diode parameters, including breakdown voltage, series resistance, junction capacitance and forward conduction mechanism.
Abstract: Present day receivers operating at millimeter and sub-millimeter wavelengths most often rely, for their first mixers, on Schottky-barrier diodes formed on epitaxial GaAs. Crucial parameters for these diodes are breakdown voltage, series resistance, junction capacitance and forward conduction mechanism. Some of these are improved, others impaired, by change of epitaxy thickness. This paper describes experience with optimizing GaAs Schottky-diode parameters by anodic oxidation thinning of GaAs epitaxial layers. Monitoring of breakdown voltage of epitaxial GaAs in anodic oxidation solution provides indication of when thinning should be stopped in subjection to the breakdown voltage specification of diodes to be made from the material. Mixer and frequency-multiplier performance superior to any previously reported have been achieved by this technique.

Patent
22 Apr 1981
TL;DR: In this article, the authors proposed a method to reduce the power consumption and occupied area of an inverter circuit by a method wherein a polycrystalline silicon p-n junction diode or a silicon Schottky junction dode is used as a load resistance element.
Abstract: PURPOSE:To reduce the power consumption and occupied area of an inverter circuit by a method wherein a polycrystalline silicon p-n junction diode or a silicon Schottky junction diode is used as a load resistance element CONSTITUTION:The polycrystalline silicon p-n junction diode or the silicon Schottky junction diode is used as the load resistance element for the inverter circuit, and the diode is connected to ensure that bias in the reverse direction is applied When an inverter transistor Q2 is conducted, a high equivalent resistance value is obtained by small area because currents in the reverse direction of the diode R2 flow through Q2 but the currents in the reverse direction of the diode R2 are little A p-n junction diode (a) of polycrystalline silicon, similarly a p-n junction diode (b), a junction diode (c) polycrystalline silicon and monocrystalline silicon and Schottky junction diodes (d), (e) can be used as the diode Thus, the power consumption and occupied area of the inverter circuit can be reduced

Patent
28 Apr 1981
TL;DR: In this article, a tuning voltage, set by variable resistor VR1 or VR2, is applied to the base of transistor TR1 by being selected corresponding to channel-selecting IC1 and channel-selection switches SW1 and SW2 and then applied to series resistance circuits R2, R3 and R4 as an emitter-follower output.
Abstract: PURPOSE:To lower the cost of production by simplifying an AFC circuit by superposing an AFC voltage on a tuning voltage to be applied to an electronic tuner. CONSTITUTION:A tuning voltage, set by variable resistor VR1 or VR2, is applied to the base of transistor TR1 by being selected corresponding to channel-selecting IC1 and channel-selection switches SW1 and SW2 and then applied to series resistance circuits R2, R3 and R4 as an emitter-follower output. An AFC voltage, on the other hand, is inputted to terminal A and then applied as the emitter-follower output of transistor TR5 to sides of series resistance circuits closer to the earth. Then, voltages led out of sides of series resistance circuits farther from the earth are outputted to the electronic tuner. As a result, it is unnecessary to provide a tuning circuit for AFC in the electronic tuner.

Journal ArticleDOI
TL;DR: In this article, an analysis of the sunlight concentration dependence of the active layer resistance in solar cells is presented, which is essentially based on well-known classical models and has been worked out for the particular case of n+/p solar cells.
Abstract: In this study, an analysis of the sunlight concentration dependence of the active layer resistance in solar cells is presented. The analysis is essentially based on well-known classical models and has been worked out for the particular case of n+/p solar cells. This study leads to a relation between the excess carrier density and series resistance change. Interpretations based on our-results explain the experimental observations of Wolf and Rauschenbach (1963) and the theoretical investigation of Bobbio et al, (1977).

Patent
26 Aug 1981
TL;DR: In this article, a destructive testing procedure in which a voltage 2.5 times the rated voltage is applied to the capacitor, at a relatively high current, is described, where the resistance in series with capacitors being tested is reduced step-by-step until the resistance value is reached such that the percentage of capacitor failures on any given sample of capacitors remains constant.
Abstract: This invention covers a destructive testing procedure in which a voltage 2.5 times the rated voltage is applied to the capacitor, at a relatively high current. The resistance in series with capacitors being tested is reduced step-by-step until the resistance value is reached such that the percentage of capacitor failures on any given sample of capacitors remains constant. Thereafter, all similar capacitors are tested at that resistance value and at 2.5 times the rated voltage. Those which do not explode exhibit remarkable reliability.

Journal ArticleDOI
01 Aug 1981
TL;DR: In this paper, the authors describe a high-yield process for the fabrication of enhancementmode MESFET integrated circuits using light-stimulated anodic oxidation followed with oxide removal as a means of recessing the gate of an FET for normally-off operation.
Abstract: The paper describes a high-yield process for the fabrication of enhancement-mode MESFET integrated circuits. The process utilises light-stimulated anodic oxidation followed with oxide removal as a means of recessing the gate of an FET for normally-off operation. The oxidation technique has an important self-limiting property allowing different amounts of GaAs to be oxidised according to local doping and thickness variations. Yields of over 85% of 11-stage ring oscillators have been obtained by this method with a standard deviation in the pinch-off voltage of 75 mV, which represents a factor of four improvement over as-grown vapour-phase epitaxial material. The recessed-gate normally-off MESFET structure also has the highest transconductance reported to date due to the reduction in parasitic series resistance. Values of gm up to 70 mS/mm have been obtained from MESFETs having gate lengths of 1.5 μm.