Showing papers on "Equivalent series resistance published in 1987"

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

Abstract: A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.

The impact of intrinsic series resistance on MOSFET scaling

Abstract: The intrinsic parasitic series resistance associated with the practical structure of a MOSFET is examined. The components considered include contact resistance, diffusion sheet resistance, spreading (injection) resistance, and accumulation layer resistance. The impact of the total resistance on MOSFET scaling is assessed, down to a channel length of 0.15 µm. The results show that, contrary to what has been claimed before, the transconductance and current of a MOSFET continue to increase as the channel length is miniaturized, although the degradation percentage-wise compared to an ideal device without series resistance continues to increase. Based on the degraded I-V characteristics and their effects on an inverter, it is shown here that for NMOS or PMOS digital circuits, the maximum degradation in speed due to series resistance is 20-35 percent compared to ideal scaling for the shortest channel considered. For CMOS circuits, the maximum degradation is reduced to 7-15 percent. In absolute terms, a loss of speed in either case due to miniaturization of channel length is not expected even down to 0.15 µm.

Submicrometer-channel CMOS for low-temperature operation

Abstract: A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n+-poly gate for n-channel and p+-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.

A model for the electric field in lightly doped drain structures

Abstract: A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor and voltage improvement, indicating the effectiveness of an LDD design in reducing the peak channel field, are used to compare LDD structures with, without, and with partial gate/drain overlap. Approximate equations have been derived that show the dependencies of the field reduction factor on bias conditions and process parameters. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor/voltage improvement and the series resistance are presented for the three cases. Structures with gate-drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate-drain offset can cause the rise of channel field and substrate current at large gate voltages. This offset is also found to be responsible for nonsaturation of drain current. The model has also been compared with two-dimensional simulation results.

Source—Drain contact resistance in CMOS with self-aligned TiSi 2

Abstract: The contact resistance between TiSi 2 and n+-p+source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10-7and 1 × 10-6Ω . cm2can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 1020/cm3. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi 2 -n+and TiSi 2 -P+interfaces.

A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's

Abstract: We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-A) n-channel implant, an n+source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-A) abrupt p-n junction, followed by a rapid thermal activation. From FET's with gates 2 µm long, a transconductance of 50 mS/mm and an output impedance of 400 Ω.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at V gs = 0 V with negligible drift.

Precision switchable gain circuit

Abstract: A switchable gain circuit includes an operational amplifier (10) which has an input leg comprised of a series resistor (20) and an MOS transistor (22). A plurality of feedback legs are formed, each comprising one or more resistors that are equal in value to the input resistor (20), and connected in series with a switch transistor. The proportion of the series resistance of the transistor in a given feedback leg to the series resistance in the transistor in the input leg is equal to the proportion of the fixed resistance in the feedback leg and input leg. The value of the series resistance of the feedback transistors therefore factors out the series resistance of the input transistor (22) in the gain calculation. This significantly reduces harmonic distortion in the output signal.

Measurement and modeling of short-channel MOS transistor gate capacitances

Abstract: A flexible electrometer method for measuring the gate capacitances of small-geometry MOS transistors is described. This technique applies to standard test transistors requiring any on-chip circuitry. Subfemtofarad accuracy and high resolution (better than 0.1 fF) have been achieved. This technique permits flexibility with regard to choices of DC biases and test devices and provides a good means of monitoring capacitance changes in the device reliability studies. The measured gate capacitances show prominent short-channel effects. A short-channel MOS transistor capacitance model has been developed which takes into account the mobility-degradation effect, velocity-saturation effect, bias-dependent fringing-field effect, and source-drain series resistance effect. Good agreement between the measured and modeled results is found. This model can be easily modified for circuit-simulation applications.

Precise capacitance measurements of high-voltage compressed gas capacitors

Abstract: The parameters affecting the capacitance measurement of compressed gas capacitors which are used as high-voltage standards are investigated. The temperature coefficient of compressed gas capacitors in the range of 2 to 3 · 10−5 K−1, as well as inevitable ambient temperature changes and gradients within high-voltage halls, were found to be mainly responsible for the limitation in the accuracy of precise capacitance measurements. A method is given to distinguish between capacitors with high- and low- voltage dependence of capacitance, without applying high voltage to them. The voltage dependence of a commercially available 120-kV, 100-pF capacitor could be considerably reduced by renewing and readjusting its electrode system. The natural frequencies of the mechanical electrode system of capacitors with rated voltages between 100 and 800 kV were found to be between 38 and 8 Hz, respectively.

Protection of integrated circuits from electric discharge

Abstract: Described is an integrated semiconductor structure for the protection from electrical discharges of electrostatic origin of particularly sensitive components of an integrated circuit. The structure is almost entirely formed directly underneath a particular input pad thus requiring a minimum useful area and is characterized by very high damaging voltage and speed of intervention because of the extremely low series resistance of the two zener junctions constituting the structure.

High Frequency Behavior of Ceramic Multilayer Capacitors

Abstract: The impedance of ceramic capacitors, made from different dielectric materials, was measured as a function of frequency from 1 MHz to 1 GHz. Most of the capacitors were of 0805 size and either end terminated or side terminated. The capacitance values ranged from a minimum of 50 pF to 100 nF. The high-frequency impedance measurements demonstrate that the inductance is a factor of two larger in end-terminated than in side-terminated ceramic muitilayer capacitors of size 0805. The inductance measured by two independent methods is 0.7 nH for the side-terminated 0805 capacitors. The inductance is only dependent on the geometry of the capacitor and independent of the dielectric material used. The capacitance and, in turn, the dielectric constant, remains constant for Z5U and X7R materials up to 100 MHz. For NPO materials the dielectric constant remains constant up to 1 GHz.

Interface states of modulation-doped AlGaAs/GaAs heterostructures

Abstract: We have used the admittance spectroscopy to investigate interface states associated with heterojunction of modulation-doped AlGaAs/GaAs FET's. Anomalous frequency dispersion of the capacitance was observed. The results of the measurements were interpreted in terms of an equivalent circuit containing a series resistance of the two-dimensional electron gas in the ungated region between the gate and the source and drain electrodes. The maximum density of the interface states was found to be 1.3 × 1012cm-2. eV-1around 0.13 eV below the E c edge of GaAs.

Three-electrode sensor for phase comparison and pulse phase adjusting circuit for use with the sensor

Abstract: Two capacitors (Cl, C2) having an identical structure and equal capacitance are used in series connection for the detection of phase difference so that ambient temperature affects both the capacitors in a similar manner to compensate for the variation in electrostatic capacitance. The sensor according to one embodiment has a lamination structure that a detection capacitor (Cl) is closely attached to a comparison capacitor (C2) providing a short time period for thermal equilibrium of both capacitors. According to another embodiment sensor, since lamination capacitors having identical structure and identical characteristic are electrically connected in series, it is now possible to locate both capacitors at desired points which are spaced apart. A member (34) having a high heat conductivity may be arranged in a space between both the capacitors to thereby reduce the time required for thermal equilibrium. In a pulse phase adjusting circuit used for processing an output signal from the sensor, a variable d.c. voltage is applied via a resistor (R3) to a junction between the detection capacitor (Cl) and a resistor (Rl), to which junction gate of an FET is connected, so as to control delay time of the pulse, making it possible to perform remote control using a variable resistor (20).

Measurement of the Characteristics of High-Q Ceramic Capacitors

Abstract: The quality factor, equivalent series resistance, and the · frequency of self-resonance are parts of the specifications of high-Q ceramic capacitors. These quantities are obtained from measurements on transmission lines with the capacitor in series or shunt. Part A: Resonant structures designed to extend the Electronics Industries Association (EIA) standard RS-483 downwards below 10 MHz and upwards above 3 GHz are discussed. For the low-frequency lines, a rule for extrapolating Q values outside the range of data is proposed. The rule is based on the frequency-dependence of the input/output coupling. The high-frequency line incorporates a method of tuning which eliminates the need for interpolation or extrapolation. It is particularly suited to measuring small parallel-plate capacitors which can be mounted on a flat shorting plate. Part B: It is shown that the first self-resonance, when viewed in terms of a series R, L, C equivalent circuit, is a poorly defined quantity. It is not always observable; it may not exist; and it may be of minor importance to design applications, it is proposed that the resonance specification of capacitors should be the first parallel resonance, defined as the first maximum in dissipation loss.

Analytical treatment of MOSFET source—Drain resistance

Abstract: Series resistance in the metal-oxide-semiconductor field-effect transistor becomes increasingly important as design rules shrink. Material properties associated with the interconnect metal, the semiconductor, and the interface separating the two regions thus assume greater importance. An analytical formulation of the resistance in terms of these material properties is thus quite desirable. We formulate and solve a two-dimensional model of current flow by the method of matched asymptotic expansions. The major utility of this solution is provided by higher order corrections to the standard transmission line model of current flow in the ohmic contact region. We find that present methods for the extraction of material properties from experimental measurements with a transmission line model analysis would be enhanced by the inclusion of higher order terms we present here.

Ion Implanted W-Band Monolithic Balanced Mixers for Broadband Applications

Abstract: An all ion-implanted monolithic broadband balanced mixer fabricated on a GaAs substrate for operation at W-band frequencies is described. A deep implanted buried n+ layer was used to minimize the diode series resistance. Ohmic contacts were formed by standard alloying of planar eutectic AuGe metallization into the n+ layer. The mixer diode structure is completely compatible with GaAs MESFET-based monolithic integrated circuit processing techniques. A conversion loss from 6.8 to 10 dB has been measured over an RF range of 75 to 88 GHz, with a LO drive of 10 dBm at 92 GHz.

Experimentally observed deviations from the superposition principle in crystalline silicon solar cells at low illuminations

Abstract: The characteristics of several silicon single crystal cells were measured in the dark and at roughly AM1.5 illumination. The circuit model parameters were extracted from the characteristics, and significant differences were observed between the dark and illuminated parameter values. These differences caused significant shortfalls in the maximum power output of the cells when compared with the predictions made using the superposition principle. Three inch cells designed for AM1.5 operation showed a shortfall of 6% at 50°C, while the concentrator cell showed a shortfall of 1%. The shortfalls increased markedly with increasing cell temperature. The possibility of artifacts being introduced is investigated and discounted. Attempts to attribute the observations to distributed series resistance effects were unsuccessful.

Charge carrier lifetime measurements on high purity silicon

Abstract: The leakage current of (strip) detectors strongly depends on the way the wafers have been processed. The charge carrier lifetime is an important parameter that can be used to describe this dependence. This paper outlines a method that can be used to measure this parameter on high purity silicon. Although the physical principles of existing methods are generally applicable, care should be taken when applying these methods on high purity silicon. The method proposed is a modification of the linear sweep method of Pierret and uses a MOS capacitor. Several anomalies make it difficult to obtain the actual generation lifetime: the fast response time of the capacitance transient, the two- and three-dimensional lateral effects, a depletion layer dependent diffusion contribution and the high series resistance. Results obtained by applying the method to differently processed wafers are presented.

Numerical analysis of GaAs epitaxial-layer Schottky diodes

Abstract: A computer simulation of GaAs epitaxial-layer Schottky-barrier diodes has been carried out. The present work extends previous drift-diffusion equation (DDE) Schottky-barrier diode simulations to very thin epilayers of GaAs as well as to higher forward bias voltages. Diodes having epitaxial layers of 0.12 and 1.0 µm were modeled with an emphasis on comparison with experiment. To achieve better agreement with experimental data an interfacial layer was included in the model, resulting in a voltage-dependent barrier height. The bias voltage at which the I-V characteristic becomes strongly nonideal is predicted to depend more on the potential drop across the interfacial layer than on the series resistances present in the devices studied. The separate contributions of the dynamic resistance of the junction and of the series resistances of the epitaxial and bulk regions to the total resistance were examined for forward biases up to 1.1 V.

Performance and analysis of amorphous silicon p‐i‐n solar cells made by chemical‐vapor deposition from disilane

Abstract: The photovoltaic performance of amorphous silicon p‐i‐n solar cells made by chemical‐vapor deposition (CVD) from disilane is reported and analyzed. Intrinsic layers were deposited at rates from 0.2 to 50 A/s at temperatures from 380 to 460 °C with and without boron doping. Device performance was insensitive to substantial differences in disilane purity. A cell efficiency of 4% was achieved. The primary limitation to higher efficiency was low fill factor ( 18 Ω cm2). Analysis of the series resistance indicated a contact‐related resistance of 4–12 Ω cm2 and a photoconductive resistance composed of intrinsic layer thickness‐independent (10 Ω cm2) and thickness‐dependent terms. Analysis of the voltage dependence of the current collection indicated a fill factor of 60% would be expected in the absence of series resistance. The maximum short‐circuit current of 12.5 mA/cm2 (normalized to 100 mW/cm2) resulted with a boron‐doped i layer deposited at 440 °C at 3.3 A/s. Modeling ...

Nontrap capacitance dispersion in Se‐Schottky diodes

Abstract: In Schottky diodes fabricated by evaporating thallium on a layer of crystallized selenium, incremental capacitance and resistance, measured at zero bias, were found to decrease considerably with frequency over the range 100 Hz to 3 MHz. This variation is interpreted in terms of series resistance of the contacts and a layer in the selenium, some 0.4 μm in thickness, near the junction which is depopulated of acceptors.

Characteristics Evaluation of Cloth-Inductor and Cloth-Transformer

Abstract: A design method of inductance and quality factor in the cloth-inductor and clothtransformer was obtained through a characteristics evaluation. The devices were evaluated by the calculation of inductance and equivalent resistance. It was a very small value of stray capacitance and leakage inductance in the cloth-inductor and cloth-transformer.For an experimental demonstration, a miniaturized 1 MHz dc-dc converter was constructed by using the cloth-inductor.

An optimum design method used for cloth-structured magnetic device

Abstract: A design method of cloth-structured magnetic device was obtained and it made clear the optimized relation between amorphous fiber and conductive fiber in size. At the design method, inductance, equivalent resistance and quality factor of cloth-structured magnetic devices were obtained analytically. It was close agreement between the measured value and the computed one. Furthermore, the stray capacitance of the device was estimated from the analysis of equivalent circuit. The analysis showed very small capacitance in the cloth-structured device.

Distortions in optical deep level transient spectroscopy on semi‐insulating GaAs with a conducting layer of finite thickness

Abstract: The use of optical deep level transient spectroscopy with intrinsic illumination to characterize deep acceptor levels in thin conducting layers on semi‐insulating GaAs is shown to generate a majority‐carrierlike peak that is, in fact, erroneous. A quantitative model is presented which explains this peak in terms of conversion of the semi‐insulating bulk GaAs below the active layer to p type due to the filling of unoccupied EL2 traps. This type of conversion induces a space‐charge region at the active layer–bulk interface which increases the resistance in series with the Schottky‐barrier depletion‐layer capacitance. The relaxation of the series resistance to its unperturbed value appears as a change in the measured capacitance, thereby creating a false majority‐carrier peak. It is emphasized that the false peak shifts the apparent position of nearby minority‐carrier peaks, thus seriously distorting the true ODLTS spectrum and making the identification of key minority‐carrier traps much more difficult.

Admittance Measurements at Epitaxial and Nonepitaxial Silicide Schottky Contacts

Abstract: We report results of an extensive study examining the usefulness of low frequency capacitance measurements for the characterization of interface states at intimate Schottky contacts. Our measurements on epitaxial as well as on nonepitaxial silicides reveal that the imaginary component of the low frequency ac-admittance is usually inductive. This inductance is caused by minority carriers that are injected by the Schottky contact and modulate the conductivity of the series resistance of the bulk silicon. The frequently reported excess capacitances (instead of inductances) that were ascribed to interface states are only reproducible when we use imperfect back-contacts to the bulk Si that add a contact resistance to the equivalent dc-circuit of the Schottky diode. Excess low frequency capacitances at intimate Schottky contacts are therefore not related to interface states but rather to the contact resistance of the back-contact.

Bi-directional circuit to interface between a low current device and high current tester

Abstract: A circuit to function as an interface between larger test instrumentation having a high capacitance, including connecting leads, and a small, low current, monolithic chip device. This interface circuit has no internal control logic, is capable of transactions in both directions and is small itself, thereby fitting close to the monolithic chip device and reflecting a relatively low capacitance load to the chip. The interface circuit includes an input buffer amplifier connected to provide a driving voltage to drive the test instrumentation in response to a voltage from the small monolithic chip device, and a sensing resistor is connected with the input buffer amplifier so that their combined equivalent resistance value is substantially equal to the resistance reflected by the test instrumentation. An operational amplifier is connected to drive a small monolithic chip device in response to a voltage across the sensing resistor that is developed by the test instrumentation.

Method for compensating for the temperature-dependent damping losses of the resonant-circuit amplitude of an oscillator, and an oscillator produced in accordance with this method

Abstract: The invention relates to a method for compensating for the temperature-dependent damping losses of the amplitude of resonance of a resonant oscillator circuit excited by a generator. In order to be able to compensate for the additional temperature-dependent losses such as eddy current losses of the coil winding and of the pot core, dielectric losses of the winding capacitance, residual losses in the ferrite of the pot core, hysteresis losses and losses due to the casting compound, added to the resistive copper losses, the rms loss resistance of the resonant circuit is used as a measure in order to create an equivalent resistance, corresponding to the rms loss resistance, in the form of a temperature sensor which is connected to the oscillator coil with good thermal conductivity and produces a damping or undamping of the amplitude of oscillation of the oscillator signal which is proportional to the temperature change.

Variable transient response control for linear integrated-circuit high-frequency amplifiers

Abstract: A variable transient response control for linear integrated-circuit high-frequency amplifiers comprises a variable equivalent resistive damping network interposed in the signal transmission path, and an electronic control circuit therefor. The resistive network includes preferably Schottky diodes having low inductance and a determinable equivalent resistance in the forward conducting condition.