Showing papers on "Equivalent series resistance published in 1996"

Microwave inductors and capacitors in standard multilevel interconnect silicon technology

Abstract: Spiral inductors and metal-to-metal capacitors for microwave applications, which are integrated on a silicon substrate by using standard 0.8 /spl mu/m BiCMOS technology, are described. Optimization of the inductors has been achieved by tailoring the vertical and lateral dimensions and by shunting several interconnect metal layers together. Lumped element models of inductors and capacitors provide detailed understanding of the important geometry and technological parameters on the device characteristics. The high quality factors of nearly 10 for the inductors are among the best results in silicon, particularly when using standard silicon technology.

Lumped parameter models for single- and multiple-layer inductors

Abstract: A method for modeling inductors under high-frequency operation is presented. The method is based on analytical approaches which can predict turn inductances, turn-to-turn and turn-to-core capacitances using physical structure of windings. Turn inductances, turn-to-turn and turn-to-core capacitances of coils are then introduced into suitable lumped parameter equivalent circuits of inductors. The overall inductance and stray capacitance can be obtained through the use of the equivalent circuits. Both single- and multiple-layer inductors are considered. The method was tested with experimental measurements. The accuracy of the results was good in most cases. The derived expressions can be useful for the design of HF inductors and can also be used for simulation purposes.

High transconductance heterostructure field‐effect transistors based on AlGaN/GaN

Abstract: We report on the fabrication and characterization of Al0.15Ga0.85N/GaN heterostructure field‐effect transistors (HFETs) with transconductance as high as 120 mS/mm and saturated current density of 0.35 A/mm for a device with a gate length and width of 1 and 100 μm. This represents one of the best results for such device. A comparison of the maximum transconductance of devices on wafers with different channel conductance is presented to analyze the factors limiting the performance. Our data indicates the series resistance between the source and drain to be the limiting factor for the maximum dc transconductance.

The bias-dependence change of barrier height of Schottky diodes under forward bias by including the series resistance effect

Abstract: Schottky barrier height shifts depending on the interfacial layer as well as a change of the interface state charge with the forward bias while considering the presence of bulk (semiconductor) series resistance are discussed both theoretically and experimentally. It has been concluded that the barrier height shift or increase in Schottky diodes is mainly due to the potential change across the interfacial layer and the occupation of the interface states as a result of the applied forward voltage. One assumes that the barrier height is controlled by the density distribution of the interface states in equilibrium with the semiconductor and the applied voltage. In nonideal Schottky diodes, the values of the voltage drops across the interfacial layer, the depletion layer and the bulk resistance are given in terms of the bias dependent ideality factor, n, different from those in literature. These values are determined by a formula obtained for Vi and Vs by means of change of the interface charge with bias.

Hall measurements and contact resistance in doped gan/algan heterostructures

Abstract: We report on doped AlGaN/GaN heterostructures with very high values of the sheet electron concentration (up to approximately 1.5×1013 cm−2), high Hall mobility (on the order of 800 cm2/Vs) and high sheet concentration‐mobility product (up to approximately 1016 1/Vs). Transmission line model measurements of the contact resistance to these layers show that series resistance is considerably reduced by doping the GaN channel. A contact resistance of 2.3 Ω mm is demonstrated for the structure with the highest sheet carrier concentration, which corresponds to ≊8.8×10−5 Ω cm2 specific contact resistance.

Effect of series resistance on the forward current-voltage characteristics of Schottky diodes in the presence of interfacial layer

Abstract: In order to make an accurate determination of Schottky diode parameters such as the ideality factor, the barrier height and the series resistance [using forward current-voltage ( I - V ) characteristics in the presence of an interfacial layer], a novel calculation method has been developed by taking into account the applied voltage drop across the interfacial layer ( V i ). The parameters obtained by accounting for the voltage drop V i have been compared with those obtained without considering the above voltage drop. To examine the consistency of this approach, the comparison has been made by means of Schottky diodes fabricated on a n -type semiconductor substrate with different bulk thickness. It is shown that the voltage drop across the interfacial layer will increase the ideality factor and the voltage dependence of the I - V characteristics. In addition, it is shown that the series resistance value increases as the semiconductor bulk thickness has been increased.

Suspended membrane inductors and capacitors for application in silicon MMIC's

Abstract: This paper considers the fabrication and modelling of suspended membrane inductors and capacitors on ordinary silicon substrates. A single post-processing etching step was added to an otherwise standard process. For both components, parasitic capacitances to ground are drastically reduced, enabling high frequency operation. Furthermore, the measured quality factor Q is demonstrably improved with respect to normally fabricated thin film components.

Cell shunt resistance and photovoltaic module performance

Abstract: The shunt resistance of solar cells in photovoltaic modules can affect module power output and could indicate flawed manufacturing processes and reliability problems. The authors describe a two-terminal diagnostic method to directly measure the shunt resistance of individual cells in a series-connected module nonintrusively, without de-encapsulation. Peak power efficiency vs. light intensity was measured on a 12-cell, series-connected, single crystalline PV module having relatively high cell shunt resistances. The module was remeasured with 0.5-, 1-, and 2-ohm resistors attached across each cell to simulate shunt resistances of several emerging technologies. Peak power efficiencies decreased dramatically at lower light levels. Using the PSpice circuit simulator, the authors verified that cell shunt and series resistances can indeed be responsible for the observed peak power efficiency vs. intensity behavior. They discuss the effect of basic cell diode parameters, i.e., shunt resistance, series resistance, and recombination losses, on PV module performance as a function of light intensity.

Series resistance calculation for the Metal-Insulator-Semiconductor Schottky barrier diodes

Abstract: An accurate way of determining the series resistance Rs of Schottky Barrier Diodes (SBDs) with and without the interfacial oxide layer using forward current-voltage (I–V) characteristics is discussed both theoretically and experimentally by taking into account the applied voltage drop across the interfacial layerVi. For the experimental discussion, the forward biasI–V characteristics of the SBDs with and without the oxide layer fabricated by LEC (the Liquid-Encapsulated Czochralski) GaAs were performed. The SBD without the oxide layer was fabricated to confirm a novel calculation method. For the theoretical discussion, an expression ofVi was obtained by considering effects of the layer thickness and the interface state density parameters on forward biasI–V of the SBDs. The valueRs of the SBD with interfacial oxide layer was seen to be larger than that of the SBD without the interfacial oxide layer due to contribution of this layer to the series resistance. According to the obtained theoretical formula, the value ofVi for the SBD with the oxide layer was calculated and it was subtracted from the applied voltage values V and then the value ofRs was recalculated. Thus, it has been shown that this new value ofRs is in much closer agreement with that determined for the SBD without the oxide layer as predicted. Furthermore, the curves of the interface states energy distribution of each sample are determined. It was concluded that the shape of the density distribution curve and order of magnitude of the density of the interface states in the considered energy range are in close agreement with those obtained by others for Au/n-GaAs Schottky diodes by Schottky capacitance spectroscopy.

CuGaSe2 solar cells with 9.7% power conversion efficiency

Abstract: Heterojunctions, such as ZnO/CdS/CuGaSe2, were fabricated for photovoltaic applications. Optimization of device structures based on monocrystalline CuGaSe2 led to the highest-to-date power conversion efficiencies for CuGaSe2 solar cells. At room temperature under 100 mW/cm2 AM1.5 illumination a maximum cell efficiency of 9.7% was achieved, given by an open-circuit voltage of 946 mV, a short circuit current density of 15.5 mA/cm2, and a fill factor of 66.5%. Preparation and performance of the optimum device are described. Current voltage characteristics dependent on illumination intensity and temperature, spectral response and electron-beam-induced current measurements were performed to determine the device parameters as well as to analyse the current transport and loss mechanisms. Tunneling, assisted by defect levels in the CdS layer, seems to play a major role. High injection effects are observed at forward bias ofV > 0.5 V or an illumination level ofP > 10 mW/cm2. Under such conditions, as well as at low temperatures, the non-zero series resistance comes into play. Effects of the shunt resistance, however, are negligible in all cases.

CuGaSe2 solar cells with 9.7% power conversion

Abstract: Heterojunctions, such as ZnO/CdS/CuGaSe2, were fabricated for photovoltaic applications. Optimiza- tion of device structures based on monocrystalline CuGaSe2 led to the highest-to-date power conversion efficiencies for CuGaSe2 solar cells. At room temperature under 100 mW/cm 2 AM1.5 illumination a maximum cell efficiency of 9.7% was achieved, given by an open-circuit voltage of 946 mV, a short circuit current density of 15.5 mA/cm 2, and a fill factor of 66.5%. Preparation and performance of the optimum device are described. Current voltage characteristics dependent on illumination inten- sity and temperature, spectral response and electron- beam-induced current measurements were performed to determine the device parameters as well as to analyse the current transport and loss mechanisms. Tunneling, assist- ed by defect levels in the CdS layer, seems to play a major role. High injection effects are observed at forward bias of V > 0.5 V or an illumination level of P > 10 mW/cm 2. Under such conditions, as well as at low temperatures, the non-zero series resistance comes into play. Effects of the shunt resistance, however, are negligible in all cases.

Modelling of tandem cell temperature coefficients

Abstract: This paper discusses the temperature dependence of the basic solar-cell operating parameters for a GaInP/GaAs series-connected two-terminal tandem cell. The effects of series resistance and of different incident solar spectra are also discussed.

Power supply using batteries undergoing great voltage variations

Abstract: A power supply using electric double layer capacitors whose output voltages undergo great variations. The power supply further includes first, second, and third switches for switching the capacitors from a parallel connection to a series connection, and a regulating circuit powered by the capacitors. As the output voltages from the capacitors drop, the regulating circuit switches the capacitors from the parallel connection to the series connection. For example, the switches are composed of semiconductor devices. The second and third switches are operated complementarily in relation to the first switch. Electric double layer capacitors producing low terminal voltages can be used. The step-up or step-down ratio can be made smaller. High voltage hazard can be avoided and the efficiency of the power supply can be improved.

A high-Q broad-band active inductor and its application to a low-loss analog phase shifter

Abstract: The proposed high-Q broad-band active inductor utilizes frequency-insensitive negative resistance to compensate constant internal losses caused by the drain-to-source conductance of the field-effect transistors (FETs), the dc bias circuit, and several other factors. The measured frequency range of the fabricated InAlAs/InGaAs/InP HEMT active inductor is 6 to 20 GHz for Q values greater than 100, and 7 to 15 GHz for Q values greater than 1000. A low-loss analog phase shifter is also fabricated at C-band. This is constructed with the active inductors, the varactor diodes and the low-loss multilayer broad-side coupler in a MIC structure. Since the constant negative resistance of the active inductors also compensates the line loss of the coupler and the varactor diodes' series resistance, the measured results show a good insertion loss performance with a large phase shift. A phase shift of more than 225/spl deg/ within a 0.8 dB insertion loss from 4.7 to 6.7 GHz, another of more than 180/spl deg/ within 1.3 dB insertion loss from 3.7 to 8.5 GHz, and one more of more than 90/spl deg/ within 1.4 dB insertion loss from 3.5 to 10.6 GHz were obtained.

Parasitic series resistance-independent method for device-model parameter extraction

Abstract: A new method is presented that permits the extraction of a semiconductor device's intrinsic model parameters from its experimental extrinsic forward I-V characteristics, independently of the parasitic resistance that might be present in series within the real device. The extraction is performed from an auxiliary function which contains the integral of the experimentally measured data. Integrating the data also serves as a smoothing procedure. The diode quality factor, reverse current and series resistance parameters of a single exponential diode model are extracted from a real p-n junction diode in order to illustrate the method.

The effect of shunt resistance on the electrical characteristics of Schottky barrier diodes

Abstract: The electrical characteristics of Schottky barrier diodes were studied considering the effect of shunt resistance. Both the DC and the AC behaviour of the device were investigated. It was found that the shunt resistance has a remarkable effect at low bias in contrast to the series resistance which influences the electrical characteristics at large bias. The standard evaluation techniques based on the DC characteristics are found to be inaccurate in the presence of the shunt resistance. Also, the AC conductance and capacitance of the device are significantly influenced, making our previously developed model limited in the presence of a shunt resistance. The well-known conductance and capacitance techniques for the characterization of these devices seem to be inapplicable at low bias because of the above-mentioned parasitic effect.

Capacitance technique for the determination of interface state density of metal-semiconductor contact

Abstract: A capacitance technique to determine the interface state density of metal—semiconductor contact is developed which takes care of interfacial oxide layer and series resistance of the device. The technique is applied to Pt- and Co-nSi contacts, and the energy distributions of interface state density are determined. For both devices, the distribution is found to be initially flat, then increasing sharply with energy.

Capacitors with very low loss: cryogenic vacuum-gap capacitors

Abstract: We report on measurements of capacitors with about 1 pF of capacitance, which have unmeasurably small leakage at very low frequencies, placing a lower bound of about 10/sup 19//spl Omega/ on the parallel resistance at an effective frequency of 1 mHz. These measurements are made possible by two themes: the use of vacuum-gap capacitors (i.e., no dielectric material, operated in vacuum), and detection of leakage using single electron tunneling (SET) electrometers, which have very high input impedance. We also report on good achieved results in time stability and lack of frequency and voltage dependence.

ESD protection circuit using zener diode and interdigitated NPN transistor

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

IC standard cell designed with embedded capacitors

Abstract: Integrated circuits running with high frequencies are a potential source for RFI (Radio Frequency Interference). To reduce RFI, on-chip dedoupling capacitors are included in the design. To gain maximum advantage of these decoupling capacitors, they should be placed close to drivers and flip-flops. In a standard cell design approach for fabrication of the ICs, capacitors are embedded below the power supply lines. These capacitors are put in special cells, called cap-cells, which are placed by the place and route software on either side of each row of standard cells. Thin oxide capacitors are preferred because they offer the largest capacitance per area. In addition, first and second metal above the capacitor are increased to form thick oxide capacitors that give additional capacitance.

An efficient method for determining threshold voltage, series resistance and effective geometry of MOS transistors

Abstract: An accurate and robust method of extracting the threshold voltage, the series resistance and the effective geometry of MOS transistors is presented. The method is based on efficient nonlinear optimization using an iterative linear regression procedure which usually converges in less than four rounds. Thereby extracted parameters are obtained from analytical expressions for the solutions to a linear system of equations whereby time consuming numerical differentiations are avoided. MOSFET parameters are explicitly identified as parameters of an underlying widely used device model that is a good approximation for operation in the linear region. The method is particularly suitable for process characterization and can be used on as few as twelve data points (three data points from each of four different size transistors). By connecting external resistors in series with the transistors, we show that the extracted values of the parameters are independent of the series resistance.

RF components implemented in an analog SiGe bipolar technology

Abstract: Several components for the design of RF transceivers on silicon substrates, developed in a manufacturable analog SiGe bipolar technology without any significant process alterations, are described. Spiral inductors in the range /spl sim/0.15-80 nH with typical maximum Q's of 3-20, MOS and MIM capacitors (1-2 pF) with Q's up to 80, and varactors with 40% tuning range and Q's of 20-50 are presented.

Black matrix for liquid crystal display

Abstract: The electric circuit of a Liquid Crystal Display normally includes a common electrode comprising a material such as indium-tin-oxide that has high resistivity and hence high series resistance. Said series resistance is significantly reduced by the design taught in the present invention wherein an electrically conductive black matrix is located so as to be in contact with the common electrode. Additionally, said design reduces the level of light reflected back in the direction of viewing, thereby improving the contrast level of the display.

Electrically adjustable resistor structure

Abstract: A resistor structure which resistance value is electrically adjusted after fabrication by a tester during the test operation so that its equivalent resistance closely approximates a desired nominal value. The resistor structure includes a main resistor and a number of trimming resistors connected in parallel. Each trimming resistor can be connected in parallel to the main resistor independently of one another via a switch, typically a pass-gate NFET device, and serially connected therewith. The switch is enabled via a control line coupled to a binary storage cell. It includes a programmable fuse that can be electrically blown by the tester. Because the resistance value of the main resistor and trimming resistors changes as a result of fabrication process variations, the trimming resistors are designed so that no matter what the equivalent resistance value of the main resistor is, there exists an appropriate combination of trimming resistors to achieve the desired nominal value. This resistor structure is well suited for IC terminator chips.

Application of double-layer capacitor technology to static condensers for distribution system voltage control

Abstract: Static condensers may be utilized to mitigate many power quality problems in distribution systems. The condenser requires some type of energy storage such as a battery, a superconducting magnetic system, or a capacitor. The use of double-layer capacitors in static condensers is examined in this paper. These capacitors are characterized by high values of capacitance and equivalent parallel resistance and low values of equivalent series resistance. Double-layer capacitor technology is discussed and equivalent circuit models are presented. Test results for a 2.3 V, 470 F double-layer capacitor are presented to demonstrate how operation in a static condenser may affect capacitor performance. Design considerations for the use of this technology in a static condenser are discussed. Operation of a static condenser employing double-layer capacitors is illustrated using EMTP.

A novel technique to determine the gate and drain bias dependent series resistance in drain engineered MOSFETs using one single device

Abstract: A new measurement method is explained for the extraction of the source and drain series resistance of drain engineered MOSFETs from their low frequency ac characteristics as a function of gate and drain bias using only one single MOSFET. Experimental results indicate, the effect of drain voltage dependent series resistance is relevant both in the ohmic and in the saturation region of the MOSFET. In addition the new measurement method is extended in such a way that it can be used to measure the series resistance as a function of gate bias only at low drain bias. Comparison of this single transistor measurement technique with other methods, needing a set of identical transistors with different channel lengths, shows that our method gives equal results. Finally attention is also given to the modeling of the series resistance in the ohmic and saturation region. For both regions simple, accurate compact model expressions have been derived.