Showing papers on "Equivalent series resistance published in 1998"
12 Oct 1998
TL;DR: In this article, the double-layer capacitor (DLC) for power applications is presented, and an equivalent circuit model consisting of three RC branches, one of them with a voltage-dependent capacitance is presented.
Abstract: The double-layer capacitor (DLC) for power applications is a new device. A simple resistive capacitive equivalent circuit is insufficient to characterize its terminal behavior. Based on physical reasoning, an equivalent circuit is proposed to provide the power electronics engineer with a model for the terminal behavior of the DLC. The equivalent circuit model consists of three RC branches, one of them with a voltage-dependent capacitance. A method to identify the circuit parameters is presented. Measurements of carbon-based DLC's for power applications are presented, analyzed, and the equivalent circuit response is compared with experimental results.
615 citations
TL;DR: In this paper, a new method to set a predictive maintenance is presented and tested on two types of converters, i.e., sound electrolytic filter capacitors and a reference system including all the converter parameters was built for the converter at its sound state, and the lifetime of these capacitors was computed.
Abstract: Electrolytic filter capacitors are frequently responsible for static converter breakdowns. To predict these faults, a new method to set a predictive maintenance is presented and tested on two types of converters. The best indicator of fault of the output filter capacitors is the increase of ESR (equivalent series resistance). The output-voltage ripple /spl Delta/V/sub o/ of the converter increases with respect to ESR. In order to avoid errors due to load variations, /spl Delta/V/sub o/ is filtered at the switching frequency of the converter. The problem is that this filtered component is not only dependent on the aging of the capacitors, but also on the ambient temperature, output current, and input voltage of the converter. Thus, to predict the failure of the capacitors, this component is processed with these parameters and the remaining time before failure is deduced. Software was developed to establish predictive maintenance of the converter. The method developed is as follows. First, a reference system including all the converter parameters was built for the converter at its sound state, i.e., using sound electrolytic filter capacitors. Then, all these parameters were processed and compared on line to the reference system, thereby, the lifetime of these capacitors was computed.
346 citations
TL;DR: In this article, a modified geometry of a solenoid type inductor using a surface micromachining technique is proposed, which has an air core and an electroplated copper coil to reduce the series resistance.
Abstract: As operation frequencies and performance requirements of wireless devices increase, the resultant demands on the performance of passive components also increase. Miniaturization of inductive components for high frequency has been a key research area to address this issue; however, in general, miniaturized integrated inductors can suffer from low Q factors and/or self-resonant frequencies when compared to their discrete counterparts. In this research, a modified geometry of a solenoid type inductor using a surface micromachining technique is proposed. This inductor has an air core and an electroplated copper coil to reduce the series resistance, and its low temperature process is suitable for various packaging applications. An important feature of the proposed inductor geometry is the introduction of an air gap between the substrate and the conductor coil in order to reduce the effects of the substrate dielectric constant. This air gap can be realized using a polyimide sacrificial layer and a surface micromachining technique. Therefore, the resulting inductor can have less substrate-dependent magnetic properties, less stray capacitance, and higher Q-factor. The measurement result shows that this inductor has high Q-factor and stable inductance over a wide range of operating frequency. Also, various effects of geometrical factors have been investigated. Various inductors with the inductance varying from 1 to 20 nH and maximum Q-factor from 7 to 60 have been fabricated and measured.
114 citations
TL;DR: In this paper, a top-gate staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors were fabricated over large-area glass substrates using a selective phosphorus-treatment (PT) of indium-tinoxide (ITO) source/drain electrodes.
Abstract: Top-gate staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were fabricated over large-area glass substrates using a selective phosphorus-treatment (PT) of indium-tin-oxide (ITO) source/drain electrodes. The ohmic contact between a-Si:H and ITO had a specific contact resistivity of about 0.18 Ωcm2. For a 100-µm channel length TFT, the source/drain series resistance contributes less than 5% of the total drain-to-source resistance. This contribution increases to about 25% for a 10-µm channel length TFT. Our study also indicated that the interface quality of a-Si:H/a-SiNx:H is amorphous silicon nitride (a-SiNx:H) and a-Si:H thickness independent and dependent, respectively. Effective interface state densities of about 1.5×1012 cm-2eV-1 and 3.2×1012 cm-2eV-1 were obtained for top-gate TFTs with a 1300 and 300 A thick a-Si:H films, respectively. Channel conductance activation energy of about 0.1 eV was measured for this top-gate TFT with 300 A a-Si:H.
93 citations
TL;DR: In this paper, a planar Al/sub 0.7/GaAs-GaAs heterostructure barrier varactor triplers were reduced from a theoretical efficiency of 10% to 3% due to self-heating.
Abstract: The conversion efficiency for planar Al/sub 0.7/GaAs-GaAs heterostructure barrier varactor triplers is shown to be reduced from a theoretical efficiency of 10% to 3% due to self-heating. The reduction is in accordance with measurements on planar Al/sub 0.7/GaAs-GaAs heterostructure barrier varactor (HBV) triplers to 261 GHz at room temperature and with low temperature tripler measurements to 255 GHz. The delivered maximum output power at 261 GHz is 2.0 mW. Future HBV designs should carefully consider and reduce the device thermal resistance and parasitic series resistance. Optimization of the RF circuit for a 10 /spl mu/m diameter device yielded a delivered output power of 3.6 mW (2.5% conversion efficiency) at 234 GHz.
69 citations
TL;DR: In this paper, the authors analyzed the components of parasitic series resistance in ULSI devices and showed that interfacial contact resistivities less than 10 −7 Ω cm 2 will be required for sub-100-nm devices in order to stay on the historical performance trend.
64 citations
Patent•
10 Aug 1998
TL;DR: In this article, an electrochemical capacitor is disclosed that features two separated, high surface area carbon cloth electrodes (16, 18) sandwiched between two current collectors (12, 14) fabricated of a conductive polymer having a flow temperature greater than 130 degrees Celsius, with the perimeter of the electrochemical being sealed with a high temperature gasket to form a single cell device.
Abstract: An electrochemical capacitor is disclosed that features two, separated, high surface area carbon cloth electrodes (16, 18) sandwiched between two current collectors (12, 14) fabricated of a conductive polymer having a flow temperature greater than 130 degrees Celsius, with the perimeter of the electrochemical being sealed with a high temperature gasket (20) to form a single cell device. The gasket material is a thermoplastic stable at temperature greater than 100 degrees Celsius, preferably a polyester or a polyurethane, and having a reflow temperature above 130 degrees Celsius but below the softening temperature of the current collector material. The capacitor packaging has good mechanical integrity over a wide temperature range, contributes little to the device equivalent series resistance, and is designed to be easily manufactured by assembly line methods. The individual cells can be stacked in parallel or series configuration to reach the desired device voltage and capacitance.
64 citations
TL;DR: An overview of the development of advanced Ti and Co self-aligned silicide (SALICIDE) processes for deep-sub-micron high performance CMOS technologies at Texas Instruments is presented in this article.
61 citations
TL;DR: In this paper, an accurate and fast method to calculate the efficiency of Cu(In,Ga)Se2 (CIGS) and CdTe thin-film solar modules is presented.
55 citations
26 Oct 1998
TL;DR: In this article, a new technique to extract ESR of decoupling capacitors is described, and a study that compares the ESL of different pad layout geometries is also presented.
Abstract: Power distribution system noise affects computer product timing performance, signal integrity and electromagnetic interference. Between 1 MHz and 1 GHz, the primary means of reducing power distribution noise is with ceramic decoupling capacitors. To achieve a certain target impedance, it is important to characterize the ESR of ceramic decoupling capacitors, as this directly determines the number of capacitors required on a board. A new technique to extract ESR is described in this paper. Another factor which determines the capacitance value of decoupling capacitors is the ESL (equivalent series inductance) associated with capacitors mounted on a PCB. A study that compares the ESL of different pad layout geometries is also presented.
53 citations
TL;DR: It is demonstrated that correction for both membrane and series resistance reduces the error in measured junctional conductance to near zero, even when membrane resistances on both sides of the gap junction are as low as 20 MΩ and the (true) junctional Conductance is as high as 100 nS.
Abstract: The dual whole-cell voltage-clamp technique is used widely for determination of kinetics and conductance of gap junctions. The use of this technique may, however, occasion to considerable errors. We have analysed the errors in steady state junctional conductance measurements under different experimental conditions. The errors in measured junctional conductance induced by series resistance alone, and by series resistance in combination with membrane resistance, were quantified both theoretically and experimentally, on equivalent resistive circuits with known resistance values in a dual voltage-clamp setup. We present and analyse a method that accounts for series resistance and membrane resistance in the determination of true junctional conductance. This method requires that series resistance is determined during the experiment, and involves some calculations to determine membrane resistance. We demonstrate that correction for both membrane and series resistance reduces the error in measured junctional conductance to near zero, even when membrane resistances on both sides of the gap junction are as low as 20 MOmega and the (true) junctional conductance is as high as 100 nS.
TL;DR: In this article, an investigation of the streamer-to-spark transition in an electrode gap of the order of 1 cm in dry air with a non-uniform field distribution is presented.
Abstract: The streamer-to-spark transition is an important sub-process of the flashover of high-voltage apparatus. In this paper an investigation of this transition in an electrode gap of the order of 1 cm in dry air with a non-uniform field distribution is presented. Parameters such as the gap distance, polarity of applied voltage and pressure were varied, but the study was concentrated upon the influence of a large series resistance (0-6 M) in the discharge circuit ( inhibited discharges). Mainly, the positive discharge was studied, but some results for negative applied voltages are also included. The main finding was that the presence of a large series resistance in the discharge circuit substantially prolonged the duration of the streamer-to-spark transition. The effect of the inhibiting series resistance seems to be that the disruptive discharge is delayed, but not prevented.
TL;DR: In this paper, the ideality factor, series resistance, leakage resistance and saturation current of a Schottky barrier diode were determined from the current-voltage characteristics of the diode.
Abstract: Simple, on-site parameter extraction methods are proposed; the ideality factor, series resistance, leakage resistance and saturation current are determined from the current-voltage characteristics of a Schottky barrier diode.
TL;DR: In this article, a general compensation technique for the extrinsic base resistance and the emitter series resistance is presented for translinear translinear circuits, and applications discussed include proportional-to-absolute temperature (PTAT) temperature sensors and bandgap references.
Abstract: The base resistance is often the primary limitation factor for the accuracy in translinear circuits. A general compensation technique for the extrinsic base resistance and the emitter series resistance is presented in this paper. The applications discussed include proportional-to-absolute-temperature (PTAT) temperature sensors and bandgap references.
25 May 1998
TL;DR: In this article, the authors developed a technique to improve the accuracy for high frequency characterization of capacitors with very low inductance values, which requires a standard calibration for a network analyzer.
Abstract: To improve the accuracy for high frequency characterization of capacitors with very low inductance values, a technique is developed. The first part of the technique requires a standard calibration for a network analyzer. Then s-parameter measurements for test fixtures and adapters are measured. A high frequency circuit model for every connector or test fixture from the calibrated port to the device under test (DUT) is then de-embedded one at a time, using the measured data as a reference and each time adding in the previously de-embedded circuit model. The difference between the measured data and the simulated data is forced to be less than 1%. This stringent requirement is necessary for obtaining the high accuracy equivalent series inductance (ESL) and resistance (ESR). The requirement also guarantees the accuracy of high frequency parasitic capacitance and resistance of a capacitor. After the high frequency circuit models for all test fixtures and adapters are found, s-parameter measurements for a capacitor mounted on a test fixture with an adapter are measured. When the circuit models for the test fixture and adapter are put together and the whole system is matched to the measured s-parameter data for the whole system, the circuit model of a capacitor has been found. In this paper, two new capacitor models and several discontinuity models are also reported. The new capacitor models are valid for the entire frequency range. The discontinuity models are fully consistent with the real physical structure of test fixtures. Different capacitors from various suppliers are characterized and the high frequency circuit models are also provided.
18 May 1998
TL;DR: In this article, a calorimetric apparatus has been designed for measurement of losses in capacitors, which is very useful for capacitors with very low losses, such as polypropylene, polycarbonate, and polyethylene terephtalate.
Abstract: A calorimetric apparatus has been designed especially for measurement of losses in capacitors. The original feature of this determination of capacitor losses lies in the use of the isothermal calorimetry and in the measurement of an electrical power and not of a temperature rise. The accuracy of the method is very good and is independent of the value of the capacitor dissipation factor, it is very useful for capacitors with very low losses. The Equivalent Series Resistance of polymer film capacitors, using polypropylene, polycarbonate, and polyethylene terephtalate, have been determined under rated voltage, in the rang 1 kHz-1 MHz, between 220 K and 370 K. The losses in the dielectric material have been separated from the losses in the metallic parts and their variations with temperature and frequency have been studied. Unlike electrical devices, the calorimetric apparatus allows us to carry out measurements of power losses in capacitors used for power electronic application (filtering, decoupling), under non-sinusoidal applied voltages.
TL;DR: An overview of the key micromachining technologies that enable communications applications for MEMS is presented with a focus on frequency-selective devices, and strategies for eliminating environmental parasites via combination of monolithic integration and encapsulation packaging are described.
Abstract: An overview of the key micromachining technologies that enable communications applications for MEMS is presented with a focus on frequency-selective devices. In particular, micromechanical filters are briefly reviewed and key technologies needed to extend their frequencies into the high VHF and UHF ranges are anticipated. Series resistance in interconnect or structural materials is shown to be a common concern for virtually all RF MEMS components, from mechanical vibrating beams, to high-Q inductors and tunable capacitors, to switches and antennas. Environmental parasites--such as feedthrough capacitance, eddy currents, and molecular contaminants--are identified as major performance limiters for RF MEMS. Strategies for eliminating them via combination of monolithic integration and encapsulation packaging are described.
TL;DR: In this article, an electromechanical description of the impedance response of thickness-shear mode quartz crystal resonators in contact with linear viscoelastic media is presented, and explicit assignments for equivalent circuit parameters (resistances, inductances, and capacitances) are derived in terms of the properties of the resonant piezoid and damping fluid medium.
Abstract: An electromechanical description of the impedance response of thickness-shear mode quartz crystal resonators in contact with linear viscoelastic media is presented. Explicit assignments for equivalent circuit parameters (resistances, inductances, and capacitances), are derived in terms of the properties of the resonant piezoid and damping fluid medium. The calculation shows that the effect of fluid elasticity is a reduction in both the equivalent resistance and inductance relative to a corresponding viscous bulk. The lower inductance is due to a reduced decay envelope for shear wave propagation into the liquid; in effect, a smaller mass of liquid is “dragged” by the crystal. The lower equivalent resistance is due to the combined effect of lower energy dissipation and enhanced recoverable energy storage within the mechanically active fluid layer near the crystal surface. Comparison of model predictions with published results on a variety of undamped, viscously damped, and viscoelastically damped crystals shows very good agreement.
TL;DR: In this paper, the authors investigated the significance of the effective contact capacitance, i.e., the interfacial capacitance during the current flow, for a wide range of stationary metal contacts operating under high charge injection rates.
Abstract: This paper investigates experimentally the significance of the effective contact capacitance, i.e., the interfacial capacitance during the current flow, for a wide range of stationary metal contacts operating under high charge injection rates. The effective capacitance of metallic interfaces depends on the ratio between the apparent contact area (which is optically determined) and the effective contact area (which injects the electronic charges). Silver contacts having series resistance values significantly less than the contact resistance were subjected to ac high current densities (up to 500 A/mm/sup 2/). The obtained i(t) and v(t) profiles were further analyzed to obtain I-V curves. Due to the phase shift between i(t) and v(t) profiles the I-V curve within a single period of the stimulating current will produce a closed loop. The area of the loop determines the interfacial electrical energy. According to the obtained results the electrical energy storage at a given metal contact, increases at: (1) higher ampacity values; (2) lower operating temperatures; (3) higher clamping forces between the joints (elastic deformation regime) each of the above parameters acting independently. The experimental results were obtained for AgSnO/sub 2/ and OFHC contacts operated in a wide temperature range, varying between -130/spl deg/C and +40/spl deg/C. The observed response of the electrical contacts is mainly characterized by the implications of the asperity contact model and dominating charge transport processes across the metallic interfaces. When standard simple equivalent circuits are used to determine contact impedance, the effective capacitance of current carrying metal contacts acquires exceptionally high values.
Patent•
12 Mar 1998TL;DR: In this article, a dielectric thin film (4) with normal electrodes (1 a, 1 b) formed on the thin film and dummy electrodes (2 a, 2 b) were provided on both side faces of the component.
Abstract: An electronic component provided with a dielectric thin film (4), normal electrodes (1 a , 1 b) formed on the thin film (4), dummy electrodes (2 a ,2 b) formed on the dielectric thin film (4) with an insulating region (20) therebetween, and auxiliary electrodes (3) provided on both side faces of the component, wherein the width of the insulating region (20) is not less than 500 times the thickness of the dielectric thin film (4) so as to improve the characteristics such as the equivalent series resistance. Thus, the deterioration of the frequency characteristics caused by the dummy electrodes can be remedied and the component can be used for a capacitor or the like.
12 Oct 1998
TL;DR: In this paper, a comparison of the main electrical criteria for polypropylene capacitors is examined through a comparison with polyethylene film capacitors, showing that the upper voltage area of the electrolytic capacitors are now covered by the polymer film capacitor.
Abstract: Over the last eight years, significant improvements have been made in the field of polypropylene capacitors. Thinner films and more sophisticated metallization techniques have allowed the range of operating voltages to be lowered to some hundreds of volts. The upper voltage area of the electrolytic capacitors is now covered by the polymer film capacitors. This overlapping is examined through a comparison of the main electrical criteria.
TL;DR: In this paper, a structure optimization of very high power density monochromatic GaAs photovoltaic cells and the theoretical prediction of their performance at irradiances ranging from 0.1 to 100 W/cm/sup 2.
Abstract: This paper deals with the structure optimization of very high power density monochromatic GaAs photovoltaic cells and the theoretical prediction of their performance at irradiances ranging from 0.1 to 100 W/cm/sup 2/. A multifaceted optimum design including the front metal grid, device size and the semiconductor layer structure is presented. The variation in efficiency depending on emitter thickness, base thickness, emitter doping and base doping is also addressed. The objective of this is the configuration of a structure suitable for working up to 100 W/cm/sup 2/ without the detrimental influence of series resistance. For this, a detailed analysis of the effect of series resistance and the quantitative determination of its different components is carried out. The optimum wavelength is 830 nm at 300 K for all the analyzed light intensities, in which a 63% peak efficiency under an irradiance of 100 W/cm/sup 2/ for a p/n structure is obtained. The temperature effect on device performance in the 273-350 K range is also studied. Finally, the influence of device processing is analyzed.
TL;DR: A quasi-TEM spectral domain approach based on the vector magnetic potential equation to calculate frequency dependent distributed inductance and the associated distributed series resistance of a microstrip on Si-SiO2 substrate is presented in this article.
Abstract: A quasi-TEM spectral domain approach based on the vector magnetic potential equation to calculate frequency dependent distributed inductance and the associated distributed series resistance of a microstrip on Si-SiO2 substrate is presented. It is shown that the calculated frequency dependent inductance and the associated resistance are in good agreement with the results obtained from rigorous full wave solutions.
TL;DR: In this paper, the effects of series resistance and diode quality factors are separately analyzed and quantified using current-voltage (IV) data gathered in situ from three photovoltaic (PV) modules.
TL;DR: In this article, the effects of source/drain series resistance and gate sheet resistance on the device speed performance were studied along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results.
Abstract: Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10/sup -7//spl Omega/-cm/sup 2/ is necessary for achieving low contact resistance in a sub-0.25-/spl mu/m fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed.
Patent•
23 Apr 1998TL;DR: In this article, a composition for forming an electrolyte for a solid electrolytic capacitor having excellent electric properties (capacitance, equivalent series resistance, dielectric loss, impedance, etc.) in a frequency zone ranging from a low frequency to a high frequency was proposed.
Abstract: A composition for forming an electrolyte for a solid electrolytic capacitor having excellent electric properties (capacitance, equivalent series resistance, dielectric loss, impedance, etc.) in a frequency zone ranging from a low frequency to a high frequency, and is capable of easily forming a high yield of the solid electrolytic capacitor having an excellent resistance to stress in the steps and a high thermal resistance, and a solid electrolytic capacitor produced from the electrolyte. The composition comprises (A) an aniline compound, (B) an organic sulfonic acid, (C) water, (D) an organic solvent, and if necessary, (E) a specified compound.
TL;DR: In this article, the open-collector method for determination of the emitter series resistance in integrated bipolar transistors is analyzed and a set of model equations is derived that provides a more accurate description of the epitaxial collector region.
Abstract: The open-collector method for determination of the emitter series resistance in integrated bipolar transistors is analyzed. Existing models do not provide the accuracy required for a correct determination of the emitter series resistance. In order to accurately describe the saturation voltage, a set of model equations is derived that provides a more accurate description of the epitaxial collector region. The measured V/sub CE/(I/sub E/) characteristic is found to depend on the properties of the collector region as well as the parasitic substrate transistor. Using the model developed, a consistent description of measurement results for different bias conditions of the collector-substrate junction is possible. With this new understanding of the open-collector method, an improved procedure to extract the emitter resistance from measurement data is developed, and results of the method applied to integrated bipolar transistors are presented.
Patent•
20 Nov 1998
TL;DR: In this article, the authors proposed a composite high frequency parts by which insertion loss is reduced and the circuit is made small and to obtain a mobile communication unit using them, which comprises a diplexer 11, 1st and 2nd high frequency switches 12, 13, and 1st, 2nd filters 14, 15.
Abstract: PROBLEM TO BE SOLVED: To obtain a composite high frequency parts by which can insertion loss is reduced and the circuit is made small and to obtain a mobile communication unit using them. SOLUTION: The composite high frequency parts 10 comprise a diplexer 11, 1st and 2nd high frequency switches 12, 13, and 1st and 2nd filters 14, 15. Then the diplexer 11 comprises 1st inductors L11, L12, and 1st capacitors C11-C15. The 1st high frequency switch 12 comprises 1st diodes D11-D13, 2nd inductors L21-L25, and 2nd capacitors C21-C25. Moreover, the 2nd high frequency switch 13 comprises 1st diodes D21, D22, 3rd inductors L31-L33, and 3rd capacitors C31-C33. Furthermore, the 1st filter 14 comprises a 4th inductor L41, and 4th capacitors C41, C42. Then the 2nd filter 15 comprises a 5th inductor L51 capacitors C51, C52. COPYRIGHT: (C)2000,JPO
25 May 1998
TL;DR: In this article, an air gap between the substrate and the conductor coil is introduced to reduce the effects of the substrate dielectric constant. And the air gap can be realized using a polyimide sacrificial layer and a surface micromachining technique.
Abstract: New solenoid-type integrated inductors for high frequency applications have been realized using a surface micromachining technique and a polymer sacrificial layer, and their geometrical characteristics have been investigated. In general, integrated inductors can suffer from low Q factors and/or self-resonant frequencies when compared to their discrete counterparts. A spiral-type inductor, one of the dominant choices as an integrated inductor, requires relatively large two-dimensional spaces. In addition, the direction of flux of the spiral type inductor is perpendicular to the substrate, which can cause more interference with underlying circuitry or other integrated passives in a vertically stacked multi-chip module (MCM). The proposed inductor in this research has an air core to reduce unwanted stray capacitance that can be added due to a magnetic core, and electroplated copper coil to reduce the series resistance. An important feature of the proposed inductor geometry is introducing an air gap between the substrate and the conductor coil in order to reduce the effects of the substrate dielectric constant. This air gap can be realized using a polyimide sacrificial layer and a surface micromachining technique. Therefore, the resulting inductor can have less substrate-dependent magnetic properties, less stray capacitance, and higher Q-factor. Inductors with different geometrical aspects, such as air gap height, core size, and number of turns, have been designed and fabricated on ceramic substrates. A variational study of these inductors has been performed to assess the impact of the geometrical aspects on the inductor performance at high frequency. The measured inductance of these inductors varies from 2nH to 20 nH, and maximum Q-factor 10-60.
TL;DR: In this article, a drain current model for submicrometer SOI MOSFETs was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and self-heating effect.
Abstract: In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries.