Showing papers on "Equivalent series resistance published in 2002"

Status quo and future prospects for metallized polypropylene energy storage capacitors

Abstract: The most important polymer film used in commercial capacitors is biaxially oriented polypropylene. Other materials, such as polyester or paper, are also used for selfhealing metallized capacitors, depending on the application. Capacitors manufactured with polypropylene have the big advantage of being less expensive than other materials, and have a very low equivalent series resistance (ESR), due to the propylene-repeating group, which results in a regular polymer chain. Electrical breakdown behavior will be analyzed in order to improve the electric field stress. Performance versus energy density will be investigated as well. We will give an overview of new proposals in the field of films, considering their reported better dielectric and mechanical performance.

Capacity limits and matching properties of integrated capacitors

Abstract: Theoretical limits for the capacitance density of integrated capacitors with combined lateral and vertical field components are derived. These limits are used to investigate the efficiency of various capacitive structures such as lateral flux and quasifractal capacitors. This study leads to two new capacitor structures with high lateral-field efficiencies. These new capacitors demonstrate larger capacities, superior matching properties, tighter tolerances, and higher self-resonance frequencies than the standard horizontal parallel plate and previously reported lateral-field capacitors, while maintaining comparable quality factors. These superior qualities are verified by simulation and experimental results.

Analysis of on-chip inductance effects for distributed RLC interconnects

Abstract: This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization techniques for distributed RLC interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. For scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes.

Comparison of various methods for calculating the AC resistance of inductors

Abstract: The paper reviews several expressions for high-frequency winding resistance of inductors proposed by several authors and compares the theoretical predictions calculated from these expressions with experimental results. It identifies the expressions that yield the most accurate prediction of the winding high-frequency resistance. The comparison shows that the method proposed by Dowell (1966) accurately predicts the AC resistance if the winding contains less than three layers. The methods proposed by several other authors accurately predict the high-frequency resistance only in certain frequency ranges. In addition, these expressions yield inaccurate results for the inductor quality factor. One expression, however, accurately predicts both the high-frequency winding resistance and the quality factor of inductors over a wide frequency range from the DC to the first resonant frequency. The paper concludes with a simple and accurate circuit model describing the frequency behavior of inductors.

Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors

Abstract: A closed-form inductance expression for compact modeling of integrated inductors is presented. The expression is more accurate than previously published closed formulas. Moreover, due to its physics-based nature, it is scalable. That is demonstrated by comparison with the measured inductance for a complete set of inductors with different layout parameters.

Reduction of DC bus capacitor ripple current with PAM/PWM converter

Abstract: Electrolytic capacitors are used in nearly all adjustable-speed drives, and they are one of the components most prone to failure. The main failure mechanisms include loss of electrolyte through outgassing and chemical changes to the electrolyte and oxide layer. All the degradation mechanisms are exacerbated by ripple current heating. Since the equivalent series resistance of electrolytic capacitors is a very strong function of frequency it must be properly modeled to accurately calculate the power loss. In this paper, a method to reduce the ripple current in a constant Volts/Hertz pulse-amplitude-modulation (PAM)/pulsewidth-modulation (PWM) converter driving an induction motor is investigated. The dc-bus voltage amplitude is reduced in proportion to speed by a buck or current stiff rectifier and the PWM modulation index is maintained at a high level to achieve a reduced ripple current below base speed. By comparison with a diode-bridge-fed PWM voltage stiff inverter, it is shown that the PAM/PWM mode of operation can lead to a significant reduction in capacitor power loss leading to increased capacitor lifetime or decreased capacitor size. The capacitor heating is analyzed using numerical and analytical techniques. Experimental results are provided to verify the analytical results.

Micromachined high-Q inductors in a 0.18-/spl mu/m copper interconnect low-k dielectric CMOS process

Abstract: On-chip spiral micromachined inductors fabricated in a 0.18-/spl mu/m digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 /spl mu/m.

Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

Abstract: Source/drain (S/D) engineering for ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented in device integration for sub-100-nm CMOS on an SOI substrate. Modeling analysis for the resistance component associated with junction profile abruptness demonstrates that a noticeable reduction in parasitic series resistance with technology generation can be achieved through junction profile slope engineering. From the experimental results of LA, it is found that PAI not only controls the ultrashallow junction depth precisely, but also reduces the laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrates in the device integration, indicating the implementation feasibility of LA to CMOS integration with an enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting substantially improved short-channel performance with higher current capability due to the box-shaped junction profile as compared with conventional rapid thermally-annealed (RTA) devices.

Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis

Abstract: Source/drain (S/D) series resistance components and device/process parameters contributing to series resistance are extensively analyzed using advanced model for future CMOS design and technology scaling into the nanometer regime The total series resistance of a device is found to be very sensitive to the variations of the sidewall thickness, the doping concentration in the deep junction region, and the Schottky barrier height of the silicide contact A prediction of series resistance trends with technology generation indicates that silicide-diffusion contact resistance and overlap resistance will be major components in the total series resistance of nanometer-scale CMOS transistors scaled according to the ITRS roadmap The key factors for challenging scaling barriers related to parasitic resistance are quantitatively examined as a function of technology scaling and it is shown that the series resistance can be substantially reduced through controlling both the abruptness of the S/D junction profile and the silicide Schottky barrier engineering

RF equivalent circuit modeling of ferrite-core inductors and characterization of core materials

Abstract: Ferrite-core inductors play an important role in electromagnetic noise suppression The radio-frequency (RF) equivalent circuit modeling of the inductor is very useful for characterizing the inductor and for noise filtering studies A technique is proposed for extracting the equivalent circuit parameters of the inductor and determining the frequency-dependent effective rod permeability as well as the intrinsic permeability of the ferrite-core material The equivalent series resistance, inductance, and the lumped shunt parasitic capacitance have been calculated versus frequency for a slug-type inductor and a toroidal-type inductor The effective rod permeability of the ferrite rod used in the slug-type inductor and the intrinsic permeability of the ferrite core used in the toroidal-type inductor have also been estimated as a function of frequency The calculated intrinsic permeability of the toroidal core agrees very well with that measured by the HP4291A RF Material Analyzer The proposed method is simple and accurate In addition, it provides an alternative way for characterizing ferrite cores at radio frequencies

Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation

Abstract: An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by division into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance, considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high-/spl kappa/ dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization.

Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part I:

Abstract: An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by dividing into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance considering the nonnegligible doping-dependent potential re- lationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high- dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization.

An improved two-frequency method of capacitance measurement for SrTiO 3 as high-k gate dielectric

Abstract: An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO/sub 3/ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics.

1/f noise in pentacene and poly-thienylene vinylene thin film transistors

Abstract: We investigate low frequency conductivity noise in the drain-source channel of organic material field-effect transistors by measuring the spectra of current fluctuations for several values of the gate voltage Vgs and drain voltage Vds and find that it is 1/f. The samples are biased in the ohmic range of the applied Vds. The relative current 1/f noise is inversely proportional to the charge carrier numbers N generated by illumination or by varying the gate-source voltage. Hooge’s empirical relation for the 1/f noise is validated for these organic semiconductors with an α≅0.01 for poly-thienylene vinylene and about 100 for pentacene thin film transistors. From geometry dependence of the noise we conclude that series resistance can be ignored for poly-thienylene vinylene field-effect transistors. However, some pentacene samples suffer from a noisy series resistance to the channel resistance. From the 1/f noise dependence on geometry and gate voltage bias we conclude that it can be used as a diagnostic tool f...

Improved Spice models of aluminum electrolytic capacitors for inverter applications

Abstract: Impedance modeling of aluminum electrolytic capacitors presents a challenge to design engineers, due to the complex nature of the capacitor construction Unlike an electrostatic capacitor, an electrolytic capacitor behaves like a lossy coaxial distributed RC circuit element whose series and distributed resistances are strong functions of temperature and frequency This behavior gives rise to values of capacitance, ESR (effective series resistance), and impedance that vary by several orders of magnitude over the typical frequency and temperature range of power inverter applications Existing public-domain Spice models do not accurately account for this behavior In this paper, a physics-based approach is used to develop an improved impedance model that is interpreted both in pure Spice circuit models and in math functions

A new wideband compact model for spiral inductors in RFICs

Abstract: A new wide-band compact model for planar spiral inductors on lossy silicon substrate is presented. Transformer loops are used in the series branch of the equivalent circuit model to include the effects of the frequency-dependent losses, in particular eddy-current loss in the silicon substrate. The new compact model and the standard 9-element model are extracted from measurement data of a typical 1.5-nH spiral fabricated on a low-resistivity CMOS substrate over a frequency range of 0.1 to 10 GHz. The frequency-dependent series resistance and inductance as well as the quality factor obtained with the new model are in excellent agreement with the measured results.

Thermal simulation for geometric optimization of metallized polypropylene film capacitors

Abstract: In this paper, the authors use an analytical model to calculate the losses in the metallized polypropylene film capacitors. The model is validated experimentally for capacitors having the same capacitance but different geometry. For each group of capacitors, a temperature distribution in the roll is assumed with the aim of optimizing its thermal performance. It appears that the heating of a long capacitor is higher than that of an equivalent flat capacitor subjected to the same electric stresses.

Maximum current in nitride-based heterostructure field-effect transistors

Abstract: We present experimental and modeling results on the gate-length dependence of the maximum current that can be achieved in GaN-based heterostructure field-effect transistors (HFETs) and metal–oxide–semiconductor HFETs (MOSHFETs). Our results show that the factor limiting the maximum current in the HFETs is the forward gate leakage current. In the MOSHFETs, the gate leakage current is suppressed and the overflow of the two dimensional electron gas into the AlGaN barrier region becomes the most important factor limiting the maximum current. Therefore, the maximum current is substantially higher in MOSHFETs than in HFETs. The measured maximum current increases with a decrease in the gate length, in qualitative agreement with the model that accounts for the velocity saturation in the channel and for the effect of the source series resistance. The maximum current as high as 2.6 A/mm can be achieved in MOSHFETs with a submicron gate.

Fluorescent lamp model based on the equivalent resistance variation

Abstract: A circuit model simulating the electrical characteristics of a fluorescent lamp operating at high frequency is proposed. The model is based on exponential approximation that represents the equivalent resistance variation as function of power, constructed by experimental results for several power levels. Simulations and experimental results are presented to verify the feasibility of the model and, moreover, an electronic ballast example using the proposed model is presented to further demonstrate its applications.

Differentially controlled varactor

Abstract: A differentially controlled variable capacitor includes two variable capacitors that are arranged effectively in parallel and receive differential input. The variable capacitors are coupled to a common node that is biased to a potential. For diode-type variable capacitors, the bias potential should ensure that the variable capacitors continue to operate as capacitors by preventing the diode device from becoming forward-biased. The differentially controlled variable capacitors are useful as tuning elements in circuits that require frequency control. A noise signal may be injected into the control signal of the variable capacitors. The effective parallel arrangement of the variable capacitors allows differential control of the effective capacitance value such that the noise signal does not alter the effective capacitance value. The differentially controlled variable capacitor is useful in circuits such as oscillators, tuned filters, and other electronic circuits that require a tuned frequency or tuned capacitance.

Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET

Abstract: A detailed investigation of the drift resistance evolution with the gate and drain biases in Lateral DMOS architectures is reported. The extractions are performed using the concept of intrinsic drain voltage, V/sub K/, applied to both simulated and measured data. Some new special test structures (MESDRIFT) have been designed and fabricated in order to investigate the DMOS bias-dependent drift resistance and experimentally confirm 2D numerical simulations. Some of the physical origins, associated with drift resistance dependence on gate and drain bias, are discussed. A simple yet efficient DMOS macro-modeling strategy is reported. It consists of combining a low-voltage BSIM model module with a bias-dependent series resistance described by a quasi-empirical mathematical expression. All LDMOS operation regimes (including quasi-saturation) are captured by the proposed expression and data measured on MESDRIFT is used to calibrate the BSIM and drift parameters. The methodology does not dependent on the drift architecture and can be applied to any similar asymmetric HV MOS devices.

Wide-band compact modeling of spiral inductors in RFICs

Abstract: A new wide-band compact modeling methodology for planar spiral inductors on lossy silicon substrate is presented. The new ideal lumped-element equivalent circuit model employs transformer loops in the series branch to include the effects of the frequency-dependent losses, in particular eddy-current loss in the bulk silicon substrate. A robust automated extraction procedure is employed to extract the element values of the new compact model. The new automated modeling methodology has been applied to a typical 1.5 nH spiral fabricated on a low-resistivity CMOS substrate. The frequency-dependent series resistance and inductance as well as the quality factor obtained with the new wideband model are in excellent agreement with the measured results over a 10 GHz bandwidth.

High capacitance anode and system and method for making same

Abstract: A method of producing electrodes for electrolytic capacitors by etching metal foil in a low pH etching electrolyte is disclosed. The low pH electrolyte is an aqueous solution, which comprises hydrochloric acid, glycerol, sodium perchlorate or perchloric acid, sodium persulfate and titanium (111) chloride. Anode foils etched according to the method of the invention maintain high capacitance gains, electrical porosity and strength. The electrical porosity of the etched foils is sufficiently high such that the overall Equivalent Series Resistance (ESR) is not increased in multilayer anodes configurations. Also described is a low pH electrolyte bath composition. Anode foils etched according to the present invention and electrolytic capacitors incorporating the etched anode foils are also disclosed.

A method to extract mobility degradation and total series resistance of fully-depleted SOI MOSFETs

Abstract: Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed.

Simulation of short LSAW transducers including electrode mass loading and finite finger resistance

Abstract: The theory for the 2-D numerical analysis of acoustic wave generation from finite length leaky surface acoustic wave (LSAW) transducer structures is presented. The mass loading of the electrodes is incorporated through the use of the finite element method (FEM). The substrate is modeled using both analytical and numerical means. The advantages of this simulation are twofold. First, it is capable of extracting the individual bulk wave conductances from the overall conductance of a given device. At large distances from the transducer, the angular distribution of power radiated relative to the substrate surface can then be calculated for each of the three possible bulk wave polarizations. The second advantage of the simulation is that the effect of finite electrode resistance is included through the use of a series equivalent resistance for each electrode in the structure. Once the resistance for each electrode in the structure has been determined, the overall effect on the device admittance is modeled by applying a constrained minimization process to the electrical boundary conditions of the transducer. To conclude the paper, the simulation will be compared against the experimental admittance of a 37-finger uniform transducer with a metallization ratio of 0.5 on 42/spl deg/ LiTaO/sub 3/. The agreement between theory and experiment is excellent.