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Equivalent series resistance

About: Equivalent series resistance is a research topic. Over the lifetime, 5335 publications have been published within this topic receiving 83362 citations. The topic is also known as: ESR.


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Journal ArticleDOI
TL;DR: In this paper, the carrier mobility of top gated graphene field effect transistors with high gate oxide capacitance was extracted from the experimental data rather than from an analytic equation, which could fit the transfer curve of a high-κ gate dielectric.
Abstract: Top gated graphene field-effect transistors were fabricated using yttrium oxide film as high-κ gate dielectric, and the gate voltage dependent drain current and gate capacitance characteristics were both measured on one graphene device. Based on the two kinds of data sets, we developed a method to extract the carrier mobility of graphene field-effect transistors, along with some other parameters, such as series resistance and residual carrier density. Prior to previous method, this method could well fit the transfer curve of graphene field-effect transistor with high gate oxide capacitance since its carrier concentration is directly obtained from the experimental data rather than from analytic equation.

36 citations

Journal ArticleDOI
TL;DR: In this paper, the series resistance effect in the temperature range of 80-400 K was investigated by considering series resistances of Schottky diodes in the case of inhomogeneous SDs and the high frequency Cm and Gm/w values were corrected for the effect of series resistance to obtain the real diode capacitance and conductance.
Abstract: The temperature dependence of capacitance-voltage (C-V) and conductance-voltage (G/w-V) characteristics of Au/polyvinyl alcohol (Co,Zn-doped)/n-Si Schottky diodes (SDs) was investigated by considering series resistance effect in the temperature range of 80–400 K. The C-V and G/w-V characteristics confirm that the series resistance (Rs) and interface state density (Nss) of the diode are important parameters that strongly influence the electric parameters of SDs. The crossing of the G/w-V curves appears as an abnormality compared to the conventional behavior of ideal SDs. It is thought that the presence of series resistance keeps this intersection hidden and unobservable in homogeneous SDs but it appears in the case of inhomogeneous SDs. In addition, the high frequency Cm and Gm/w values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance and conductance.

36 citations

Journal ArticleDOI
TL;DR: In this paper, the effect of series resistance on the non-ideal silicon Schottky diode (SSD) in process fabrication has been investigated and two types of diodes with high resistivity silicon bulk have been prepared.

36 citations

Journal ArticleDOI
13 Jun 2005
TL;DR: In this article, an expanded physically based model for multiple-metal stacked inductors is presented, which expands on previous research to show the effects and limitations of stacking two, three, and four metal layers in a five-metal-layer process.
Abstract: Modern analog circuits are heavily dependent on inductor performance, where the poor inductor quality factor (Q) of silicon processes leads to degradation in circuit efficacy, especially at RF and microwave frequencies. Several techniques have been proposed to enhance the Q of integrated on-chip inductors, but the most effective method of Q improvement is to lower the series resistance by increasing the inductor metal thickness. This paper presents the most cost-effective method of achieving a thick metal by using a standard 0.18-/spl mu/m multilayer BiCMOS process. An expanded physically based model for multiple-metal stacked inductors is presented, which expands on previous research to show the effects and limitations of stacking two, three, and four metal layers in a five-metal-layer process. The excellent accuracy of this geometrical model is illustrated with respect to a range of inductor designs showing that an improvement in Q of more than 50% may be achieved. Due to the increased parasitics in multilayer structures, the Q improvement is very frequency dependent, which is clearly predicted with the expanded model. The predictive capability of the model is further used to provide detailed insight into the effectiveness of a patterned ground shield for different substrate characteristics. This predictive ability will contribute greatly to first time right inductor designs and eliminate the expensive and time-consuming fabrication iterations required to fine tune other inductor models.

36 citations

Journal ArticleDOI
TL;DR: The proposed technique for monitoring of power extraction efficiency is implemented in the existing digital processor/controller used for MPP tracking, thereby avoiding additional circuits/sensors and mathematical model relating the capacitance and ESR values to the PEE is derived.
Abstract: Electrolytic capacitors are popularly used in single-phase grid-feeding solar photovoltaic (PV) inverters to suppress the second harmonic and switching frequency voltage ripples. With aging equivalent series resistance (ESR) of capacitor increases and its capacitance value decreases, which lead to increase in dc-link voltage ripple. Oscillations in PV operating point around its maximum power point (MPP), results in reduction of average output power and revenue generated. To address this, frequent replacement of capacitors are required, which may lead to increased cost. Therefore, capacitors must be replaced at an optimal period to ensure maximum earnings. To realize this, a technique for monitoring of power extraction efficiency (PEE) is proposed in this paper. Further, criteria for replacement of capacitor based on the measured values of PEE is suggested. Mathematical model relating the capacitance and ESR values to the PEE is derived. Effect of variation in temperature and solar radiation on PEE is discussed. Detailed simulation studies are carried out using MATLAB-Simulink. A scaled down laboratory prototype of inverter is developed. The proposed technique is implemented in the existing digital processor/controller used for MPP tracking, thereby avoiding additional circuits/sensors. PEE estimated by simulation and experimentation are found to be within 1% of each other.

36 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023121
2022235
2021126
2020170
2019171
2018206