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Equivalent series resistance

About: Equivalent series resistance is a research topic. Over the lifetime, 5335 publications have been published within this topic receiving 83362 citations. The topic is also known as: ESR.


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Journal ArticleDOI
TL;DR: An original and accurate online scheme applied to estimate the output capacitor of the flyback converter is put forward and an online mathematical model for the equivalent series resistance (ESR) and capacitance (C) is derived.
Abstract: Since electrolytic capacitors are primarily responsible for breakdowns in power electronics converters and have the trait of high failure rate, their reliability is a tremendous concern. Consequently, an appropriate monitoring as well as fault diagnosis system should be laid emphasis on. In this paper, an original and accurate online scheme applied to estimate the output capacitor of the flyback converter is put forward. By analyzing the voltage ripple of the output electrolytic capacitor in detail, an online mathematical model for the equivalent series resistance (ESR) and capacitance (C) is derived. A trigger circuit and an isolated amplification circuit are designed to catch the output voltage ripple values at certain instants of switching cycle, which are sent to digital signal processor for the calculation of ESR and C. The proposed scheme is noninvasive as no extra current sensor is needed. In order to verify the feasibility of the scheme, a prototype of the online monitoring system is built and experiments are conducted.

31 citations

Proceedings ArticleDOI
09 Nov 2010
TL;DR: In this paper, the changes in the ripple current for an electrolytic capacitor used in the dc-side of a single-phase rectifier circuit when subjected to input voltage fluctuations were evaluated.
Abstract: This paper evaluates the changes in the ripple current for an electrolytic capacitor used in the dc-side of a single-phase rectifier circuit when subjected to input voltage fluctuations. The study has been undertaken in order to analyse the potential impact on capacitor lifetime. The key effect is that the capacitor ripple current, as a consequence of voltage fluctuations, increases dramatically and this phenomenon keeps deteriorating as the frequency of the voltage fluctuations increases. Simulations and experimental work confirm this phenomenon. Since the power loss and temperature rise are dependent on the capacitor equivalent series resistance (ESR) and ripple current components, an increase in ripple current under voltage fluctuation conditions is likely to accelerate this process, resulting in a reduced lifetime.

31 citations

Journal ArticleDOI
TL;DR: In this paper, a methodology is developed for the extraction of cell-level properties from the analysis of differential IV response in a solar module with series connected cells, and the shunt resistance and short circuit current of individual cells can be determined from a peak in the module differential resistance with cells that are partially shaded.
Abstract: A methodology is developed for the extraction of cell-level properties from the analysis of differential IV response in a solar module with series connected cells. Through a combination of simulation and experimental verification we show that the shunt resistance and short circuit current of individual cells can be determined from a peak in the module differential resistance with cells that are partially shaded. The magnitude of the peak is equal to the shunt resistance of the cell for small values of shunt resistance. The current at which the peak occurs is proportional to the product of the short circuit current and the shading factor of the particular cell. With this methodology, we are able to measure degradation of 72 individual cells in a single commercial module after a high temperature/high humidity/high voltage stress test. Therefore, the statistics of degradation in this test were improved 72-fold. Copyright # 2010 John Wiley & Sons, Ltd.

31 citations

Journal ArticleDOI
TL;DR: In this paper, it was shown that P-implantation forming n+regions followed by post-metallization annealing (PMA) at a moderate temperature of 200°C is very efficient in reducing the resistance of the Al contacts to negligibly small values.
Abstract: Amorphous silicon thin-film field-effect transistors have been made with a staggered electrode structure. In this structure we distinguish two separate contributions to the total contact resistance, namely, the Al/a-Si:H barrier itself and the bulk resistance of the underlying a-Si:H layer. Concerning the first contribution it was found that a P-implantation forming n+regions followed by post-metallization annealing (PMA) at a moderate temperature of 200°C is very efficient in reducing the resistance of the Al contacts to negligibly small values. The second contribution, i.e., the bulk resistance, implies a variable series resistance in field-effect (FE) measurements. Thin-film transistors (TFT's) with different gate lengths were used for the first time to determine this residual series resistance R res .

31 citations

Proceedings ArticleDOI
29 Nov 2001
TL;DR: In this article, the authors present an overview of the SiGe junction technology designed to meet the demands of the future technology nodes down to 30 nm, which is based upon selective deposition of boron or phosphorus doped SiGe in source/drain areas isotropically etched to the desired junction depth.
Abstract: Future CMOS technology nodes bring new challenges to formation of source/drain junctions and their contacts to limit their series resistance contribution to ten percent of the device channel resistance. This requires not only extremely low junction sheet resistance values but also super abrupt doping profiles and contact resistivities that can not be obtained with the existing self-aligned silicide technology. In this paper, we present an overview of the SiGe junction technology designed to meet the demands of the future technology nodes down to 30 nm. The technology is based upon selective deposition of boron or phosphorus doped SiGe in source/drain areas isotropically etched to the desired junction depth. The technology is limited to temperatures below 800/spl deg/C. Hence; it is also compatible with future high-/spl kappa/ gate stacks, which can not withstand higher temperatures. The results indicate that the technology offers great promise in meeting the demands of the end-of-the-roadmap devices.

31 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023121
2022235
2021126
2020170
2019171
2018206