Topic
Equivalent series resistance
About: Equivalent series resistance is a research topic. Over the lifetime, 5335 publications have been published within this topic receiving 83362 citations. The topic is also known as: ESR.
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IBM1
TL;DR: In this article, a new integrated methodology for the accurate extraction of source/drain (S/D) series resistance components with emphasis on the spreading and contact resistance elements is presented, and detailed extractions of lateral extension doping abruptness and silicide specific contact resistance are made directly from 90nm-node SOI MOSFET characterization.
Abstract: A new integrated methodology for the accurate extraction of source/drain (S/D) series resistance components with emphasis on the spreading and contact resistance elements is presented. For the first time, detailed extractions of lateral extension doping abruptness and silicide specific contact resistance are made directly from 90nm-node SOI MOSFET characterization. The spreading resistance due to the lateral doping gradient is found to be a key component contributing to total parasitics, and the doping gradient engineering and scaling of specific contact resistance must be employed to overcome this parasitic limitation in future nanoscale CMOS performance roadmap
28 citations
08 Sep 1997
TL;DR: In this article, a simple-to-implement semi-empirical model for circuit-level simulation of the MOS breakdown region, with application in ESD-protection circuit design, is presented.
Abstract: This paper presents a simple-to-implement, semi-empirical model for circuit-level simulation of the MOS breakdown region, with application in ESD-protection circuit design. A new formulation for the multiplicative factor M, used to model avalanche current generation, shows good convergence properties when used in circuit simulators. The effects of source/drain series resistance, substrate resistance, and the parameters of the new M expression are described. We describe how to calibrate the parameters for an NMOS device. Finally, we compare the simulated results with experimental data.
28 citations
TL;DR: In this paper, the authors show that the nanowire located at the bottom of the stack is farthest away from the source/drain silicide contacts and suffers from higher series resistance as compared to the nanwires that are higher up in the stack.
Abstract: Vertically stacked nanowire field effect transistors currently dominate the race to become mainstream devices for 7-nm CMOS technology node. However, these devices are likely to suffer from the issue of nanowire stack position dependent drain current. In this paper, we show that the nanowire located at the bottom of the stack is farthest away from the source/drain silicide contacts and suffers from higher series resistance as compared to the nanowires that are higher up in the stack. It is found that upscaling the diameter of lower nanowires with respect to the upper nanowires improved uniformity of the current in each nanowire, but with the drawback of threshold voltage reduction. We propose to increase source/drain trench silicide depth as a more promising solution to this problem over the nanowire diameter scaling, without compromising on power or performance of these devices.
28 citations
01 Dec 2006
TL;DR: In this article, the authors present new results on silicon I-MOS devices, obtained by an adaptation of a conventional CMOS process, where the source and the drain are doped of opposite type.
Abstract: This papers presents new results on silicon I-MOS devices, (where the source and the drain are doped of opposite type) obtained by an adaptation of a conventional CMOS process. Fabricated devices are fully functional down to 55nm of gate length, but the influence of the gate becomes strongly reduced for shorter devices due to technological limitations. Nevertheless, the smallest device, with a 17nm gate length and with an avalanche threshold of 5.3V, is reported. The corresponding output current-voltage features an equivalent resistance as low as 66 Omegamiddotmum. For all devices, the maximum current is only limited by the contacts destruction, positioning the measured value of 4700 muA/mum among the highest ever reported for a MOS device. In addition, it is shown that the extrapolated Ion/Ioff figure of merit is close to complying with the specifications imposed to the HP flavor of the ITRS'05 roadmap
28 citations
21 Jun 2010
TL;DR: In this paper, the capacitance and ESR values of commercially available capacitors at 77 K and 4 K were analyzed for low-imperformant low impedance sensors with TES.
Abstract: Commercially available capacitors are not specified for operation at 77 K or 4 K, and some devices showed a dramatic decrease of capacitance at cryogenic temperature. Furthermore, for voltage biasing of cryogenic low impedance sensors it is very important to know parasitic resistance. In this case, the parasitic Equivalent Series Resistance (ESR) of the capacitor used for the AC-biasing is a bottleneck of the voltage biasing. Involved in TES development and SQUID multiplexing, we have characterized the capacitance and the ESR values of some commercially available capacitors at 77 K and 4 K.
28 citations