Equivalent series resistance

About: Equivalent series resistance is a research topic. Over the lifetime, 5335 publications have been published within this topic receiving 83362 citations. The topic is also known as: ESR.

Improved Switching Stability and the Effect of an Internal Series Resistor in HfO 2 /TiO x Bilayer ReRAM Cells

Abstract: Bipolar redox-based resistive random-access memory cells are intensively studied for new storage class memory and beyond von Neumann computing applications However, the considerable variability of the resistance values in ON and OFF state as well as of the SET voltage remains challenging In this paper, we discuss the physical origin of the significant reduction in the switching variability of HfO2-based devices achieved by the insertion of a thin TiO x layer between the HfO2 layer and the oxygen exchange metal layer Typically, HfO2 single layer cells exhibit an abrupt SET process, which is difficult to control In contrast, self-compliance effects in the HfO2/TiO x bilayer devices lead to an increased stability of SET voltages and OFF-state resistances The SET process is gradual and the RESET becomes abrupt for higher switching currents Comparison of the experimental data with simulation results achieved from a physics-based compact model for the full description of the switching behavior of the single layer and bilayer devices clearly reveal three major effects The TiO x layer affects the temperature distribution during switching (by modifying the heat dissipation), forms an additional series resistance and changes the current conduction mechanism in the OFF state of the bilayer device compared to the single layer device

Top-Gate Staggered Amorphous Silicon Thin-Film Transistors: Series Resistance and Nitride Thickness Effects

Abstract: Top-gate staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were fabricated over large-area glass substrates using a selective phosphorus-treatment (PT) of indium-tin-oxide (ITO) source/drain electrodes. The ohmic contact between a-Si:H and ITO had a specific contact resistivity of about 0.18 Ωcm2. For a 100-µm channel length TFT, the source/drain series resistance contributes less than 5% of the total drain-to-source resistance. This contribution increases to about 25% for a 10-µm channel length TFT. Our study also indicated that the interface quality of a-Si:H/a-SiNx:H is amorphous silicon nitride (a-SiNx:H) and a-Si:H thickness independent and dependent, respectively. Effective interface state densities of about 1.5×1012 cm-2eV-1 and 3.2×1012 cm-2eV-1 were obtained for top-gate TFTs with a 1300 and 300 A thick a-Si:H films, respectively. Channel conductance activation energy of about 0.1 eV was measured for this top-gate TFT with 300 A a-Si:H.

High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz

Abstract: High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.

Compact model for short channel symmetric doped double-gate MOSFETs

Abstract: A new compact model for currents in short channel symmetric double-gate MOSFETs is presented which considers a doped silicon layer in the range of concentrations between 10 14 and 3 � 10 18 cm � 3 . The mobile charge density is calculated using analytical expressions obtained from modeling the surface potential and the difference of potentials at the surface and at the center of the Si doped layer without the need to solve any transcendental equations. Analytical expressions for the current–voltage characteristics are presented, as function of silicon layer impurity concentration, gate dielectric and silicon layer thickness, including variable mobility. The short channel effects included are velocity saturation, DIBL, VT roll-off, channel length shortening and series resistance. Comparison of modeled with simulated characteristics obtained in ATLAS device simulator for the transfer characteristics in linear and saturation regions, as well for as output characteristics, show good agreement within the practical range of gate and drain voltages, as well as gate dielectric and silicon layer thicknesses. The model can be easily introduced in circuit simulators.