Equivalent series resistance

About: Equivalent series resistance is a research topic. Over the lifetime, 5335 publications have been published within this topic receiving 83362 citations. The topic is also known as: ESR.

Effects of self-heating on planar heterostructure barrier varactor diodes

Abstract: The conversion efficiency for planar Al/sub 0.7/GaAs-GaAs heterostructure barrier varactor triplers is shown to be reduced from a theoretical efficiency of 10% to 3% due to self-heating. The reduction is in accordance with measurements on planar Al/sub 0.7/GaAs-GaAs heterostructure barrier varactor (HBV) triplers to 261 GHz at room temperature and with low temperature tripler measurements to 255 GHz. The delivered maximum output power at 261 GHz is 2.0 mW. Future HBV designs should carefully consider and reduce the device thermal resistance and parasitic series resistance. Optimization of the RF circuit for a 10 /spl mu/m diameter device yielded a delivered output power of 3.6 mW (2.5% conversion efficiency) at 234 GHz.

Impedance spectroscopy of thin-film CdTe/CdS solar cells under varied illumination

Abstract: The electrical properties of CdTe/CdS solar cells grown by metal organic chemical vapor deposition were investigated by a technique of impedance measurements under varied intensity of AM1.5 illumination. A generalized impedance model was developed and applied to a series of CdTe/CdS cells with variations in structure and doping. The light measurements were compared to the conventional ac measurements in dark under varied dc bias, using the same methodology for equivalent circuit analysis in both cases. Detailed information on the properties of the device structure was obtained, including the properties of the main p-n junction under light, minority carrier lifetime, back contact, as well as the effect of the blocking ZnO layer incorporated between the transparent conductor and CdS layers. In particular, the comparison between samples with different chemical concentrations of As has shown that the total device impedance and the series resistance are strongly increased at lower As densities, resulting in the lower collection current and efficiencies. At the same time the minority carrier lifetime was found to be one order of magnitude larger for the lowest value of As density, when compared to the optimized devices.

CuGaSe2 solar cells with 9.7% power conversion efficiency

Abstract: Heterojunctions, such as ZnO/CdS/CuGaSe2, were fabricated for photovoltaic applications. Optimization of device structures based on monocrystalline CuGaSe2 led to the highest-to-date power conversion efficiencies for CuGaSe2 solar cells. At room temperature under 100 mW/cm2 AM1.5 illumination a maximum cell efficiency of 9.7% was achieved, given by an open-circuit voltage of 946 mV, a short circuit current density of 15.5 mA/cm2, and a fill factor of 66.5%. Preparation and performance of the optimum device are described. Current voltage characteristics dependent on illumination intensity and temperature, spectral response and electron-beam-induced current measurements were performed to determine the device parameters as well as to analyse the current transport and loss mechanisms. Tunneling, assisted by defect levels in the CdS layer, seems to play a major role. High injection effects are observed at forward bias ofV > 0.5 V or an illumination level ofP > 10 mW/cm2. Under such conditions, as well as at low temperatures, the non-zero series resistance comes into play. Effects of the shunt resistance, however, are negligible in all cases.

Electrolytic capacitors with a polymeric outer layer and process for the production thereof

Abstract: The invention relates to a process for the production of electrolytic capacitors with low equivalent series resistance and low residual current consisting of a solid electrolyte made of conductive polymers and an outer layer containing conductive polymers, to electrolytic capacitors produced by this process and to the use of such electrolytic capacitors.

Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

Abstract: Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. I/sub dsat/ can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.