Showing papers on "Error detection and correction published in 1969"

Error detection and correction system with statistically optimized data recovery

Abstract: A statistically optimized data recovery apparatus in a system having data storage and retrieval means, said apparatus including error detection means, a plurality of error correction means, first schedulers for scheduling a plurality of error correction attempts, and a second scheduler and a parameter variation means, said second scheduler providing for ordered selection of the first scheduler, and said parameter variation means providing for variation of parameters of said retrieval means, in an attempt to recover data in error.

Fast decode character error detection and correction system

Abstract: Apparatus for detecting and correcting errors in a digital computer storage system is disclosed Data is encoded using a generalized Reed-Solomon encoder Error detection circuitry including power sum calculating devices are used for detection of data in error The error correction portion of the invention includes an improved decoding scheme for determining the location and magnitudes of errors within the data and has a very low average correction time Means are provided for determining the starting area of a data block in the presence of errors in the starting area Further means are provided for detecting a cyclic shift in a data character which, under normal conditions, would appear as an acceptable code word even though in error

Error detection scheme for memories

Abstract: A method and apparatus for detecting errors occurring as a result of faulty memory operation. By storing every data word in an addressable memory at an address therein having a parity with a fixed predetermined relationship to the parity of the said data word, errors occurring in the memory may be detected. By incorporating an extra bit in the memory word, the error can be isolated and by incorporating two extra bits, double word readout errors may be detected.

Memory with error correction for partial store operation

Abstract: This invention provides coding circuits for storing words in a memory in an error correction code and for operating with an associated system in which data is provided with error detecting parity check bits. The coding circuits include means for locating an incorrect bit of a memory word and for updating the error correction bits to correspond to the corrected word.

Vehicle subsystem monitors

Abstract: A multiple error detection system utilizing light-emitting diodes to form a character representation in response to a given error signal input.

Coding for error control

Abstract: Tutorially presented are theoretical and practical concepts that underlie error-control coding for data computing, storage, and transmission systems. Emphasis is on cyclic codes, the most deeply studied and widely used of the many available codes. Operations of typical binary shift registers illustrate the encoding and decoding processes. Strategic considerations for applying coding to computer-communication systems are discussed. Actual applications further exemplify the basis for code selection.

Method and apparatus for triple error correction

Abstract: The invention relates to a simplified method for extracting triple error correction information from a (23, 12) BoseChaudhuri code which is the Golay code. In a 23-bit word having three or less errors, the method provides correction on a bit-bybit basis. Each bit is assumed to be in error and corrected, the remaining 22 bits are then interrogated for two or less errors. Also disclosed is the apparatus for extracting the error correction information from the Golay code in a Bose-Chaudhuri code is comprised of a check word generator and shifting means, decoder circuitry, false error indication inhibit circuitry, control circuitry and error action circuitry.

High speed data transmission system utilizing nonbinary correlative techniques

Abstract: A digital data transmission system which significantly increases the transmission rate of a binary data signal over a band limited transmission channel employs correlative techniques utilizing novel precoding for converting a binary input signal into a multilevel nonbinary correlative signal which is transmitted. Each level of the transmitted signal, seven being required to achieve a factor of eight improvement in transmission rate, represents a particular combination of the original binary digits, and introduction of correlative properties at the transmitter permits the original binary data to be recovered at the receiver with standard logic circuits without reference to the past history of the waveform. The correlative properties of the transmitted signal also permit error detection without adding redundant digits at the transmitter end. The bit speed capability of the concept is not limited to eight times that of a binary system but, in general, is equal to 21og2Q per Hertz in carrier applications, where Q is equal to the number of levels of a noncorrelative nonbinary signal and is an integer greater than two.

Error Detection for Partial-Response Systems

Abstract: An error detector for data transmission systems using a partial-response signaling format is described. The basis of the error detector is a partial-response correlation constraint. An approximate expression for performance is presented, and it is noted that calculated and experimental performance agree for error rates less than 10-3.

Binary Decoding Extended to Nonbinary Demodulation of Phase Shift Keying

Abstract: The required energy per information bit E_{B}/N_{o} to achieve a specified error probability with a binary error correcting code is reduced by retaining partial knowledge of digit amplitudes. Quantization to three or four levels is the minimum step of demodulator complexity beyond hard decisions. A simple extension of binary decoding is described which achieves a large part of the maximum improvement theoretically available with unquantized demodulation. The usual decoding process is modified only to the extent that two decoding operations are performed, rather than one. Also, storage is needed to compare the two resulting words to select the preferred one. With four-level demodulation, an improvement of more than one decibel is demonstrated even for small code word lengths over a nonfading phase shift keyed (PSK) coherent channel with white Gaussian noise.

Error correcting code device for parallel-serial transmissions

Abstract: Data signals are encoded in an (n,k) cyclic code and checked for errors and corrected. The encoding and correction decoding apparatus includes an n-k stage parallel input parallel feedback shift register adapted to process the data digit signals in groups of c digits where the number c is greater than n-k. An example of implementation is disclosed for the specific case: n 72, k 64, and c 18, illustrating that encoding and/or error check decoding are completed in only 4 ( n/c) parallel shifts and that error correction decoding is accomplished in a maximum of only 3 additional parallel shifts timed to coincide with the handling of the data signals.

Optimum error-correcting code device for parallel-serial transmissions in shortened cyclic codes

Abstract: Errors in transmitted shortened cyclic code words are detected and corrected by unusually simple apparatus at a receiver and transmitter connected together by a bus. A 72-bit parallel code word, actually comprising a 64-bit data portion and an eight bit checking portion, is conceptually expanded and treated as if it were 108 bits long. At both the transmitter and receiver, the word is split into four sequential groups and sent to an eightposition parallel feedback shift register via an 18-bit bus and intermediate circuits. Each bit on the bus is assigned a channel and the register positions are connected to selected channels through summing circuits, and to each other through feedback circuits, of varying complexity. At the transmitter, the final contents of the register are the checking portion of the code word. At the receiver, if there is an error, the final contents of the shift register indicate which bit in the data portion of the code word must be corrected. The eighteen bits on the bus are connected to selected ones of 27 conceptual channels of which 18 are real (connected to the bus) and nine are phantoms (not connected to anything). While no summing circuit connections are required for the phantom channels, each one of the 27 conceptual channels nevertheless has associated with it a known number of circuit connections. The amount of hardware is greatly reduced by connecting to the bus those conceptual channels requiring the least number of circuit connections and designating as phantoms those conceptual channels which would have required the most summing circuit connections. The total complexity of the feedback circuits and associated error location and correction circuits are similarly lessened.

Digital data error detection apparatus

Abstract: IN A DIGITAL INFORMATION TRANSFER SYSTEM INCORPORATING A CYCLIC CODE ERROR CHECKING SCHEME, AN APPARATUS FOR SENSING ERRORS RESULTING FROM AN END-AROUND SHIFT COMPLEMENTS THE FIRST BIT OF SERIALLY TRANSMITTED DATA AND APPENDS IT TO THE TRANSMITTED MESSAGE, THEREBY PROVIDING ADDITIONAL INFORMATION BY WHICH TO SENSE ERRORS NOT OTHERWISE DETECTABLE BY A CYCLIC CHECKING SCHEME ALONE.

Error detection in multilevel transmission

Abstract: Error detection in multilevel partial response correlation code transmission is achieved by maintaining separate running sums of discrete sets of related pulses. Each sum is monitored for violation of particular constraints characteristic of the code and both error indicator and sum correction signals are generated.

Binary Synchronous Communications

Abstract: Binary synchronous communications, in particular the line-control functions, are described. These functions are independent of the devices transmitting and receiving, the mode of transmission, and the transmission code. A mode known as transparent transmission allows the transmission of data, independent of its bit structure. The various aspects of transmission are discussed, including station control, transmission formating, error detection, and error recovery. In addition, the communication control characters are described in detail.

Data input error detection and correction procedures

Abstract: : The study is an examination of the input data error problem in computerized information systems. The area of concern is the detection and correction of input data errors resulting from human recording during the initial collection of the data. This research attempts to remove some of the mystery surrounding the input error problem. A system for classifying errors by type is developed; attention is paid to the kinds of errors which can be made or introduced at various levels in the data generation-data processing chain. More important, these levels and their potential use to managers and researchers alike provide a conceptual framework in which intelligent discussions concerning the error process can be formulated. The concept of data worth alone provides a significant step forward in building an intelligent detection and correction process. The study develops a systematic procedure--a model--for evaluating the various detection and correction alternatives. The final evaluation of the detection and correction procedures to be used in the system is based on cost. This is not displacement cost, but cost associated with improved operations through more accurate information. The value of information is the worth of the data, and the worth of the data is the data accuracy problem. The major contributor to data accuracy is formal procedures for input error detection and correction. This study has developed these formal procedures.

Error correction in sampled-data circuits

Abstract: Error correction in modems and similar sampled-data circuits that have outputs representable as outputs of a linear circuit with integer-valued impulse response when the integer-valued input sequence is subject to predetermined constraints. Integervalued tentative decisions and reliability information are formed and stored. A correction is made upon detection, on the basis of the constraints, of an error in the tentative decisions. Shown also are: an inverse linear circuit for detecting decision errors according to whether its outputs satisfy the constraints, with means to combat propagation of the error in the inverse circuit; reliability information in the form of magnitude and sign of apparent errors, especially storing only the extreme values of apparent errors in the sequence under review; constraints in form of predetermined finite range of integers and detection with an inverse circuit on basis of values falling outside of the finite range, also combating propagation by replacement of erroneous value with closest substitute satisfying the constraints; and impulse responses of the form 1 + OR - Dn, where n integer, and division of tentative decisions and memory into related groups.

Algebraic Coding and Digital Redundancy

Abstract: The techniques of coding theory are used to improve the reliability of digital devices. Redundancy is added to the device by the addition of extra digits which are independently computed from the input digits. A decoding device examines the original outputs along with the redundant outputs. The decoder may correct any errors it detects, not correct but locate the defective logic gate or subsystem, or only issue a general error warning. Majority voting and parity bit checking are introduced, and computations are made for several binary addition circuits. A detailed summary of coding theory is presented. This includes a discussion of algebraic codes, binary group codes, nonbinary linear codes, and error locating codes.

Data recovery in a photo-digital storage system

Abstract: A data-recovery feature has been developed for recovering electron-beam recorded information which is microscopic in dimension and has been partially obliterated by flaws in a photographic-film recording medium. This feature provides (1) backup procedures that exploit redundancies in the recording format for the synchronization and identification of data, (2) coding for error detection and correction of 5 independent characters in5 0 data character lines, (3) variation of machine parameters that affect reading performance, and (4) statistically optimized schedules for applying a variety of recovery techniques. Error rate is reduced from one error line in about 100 lines to less than one error line in 2.7 × 106 lines.

Error-detecting system for data-processing circuitry

Abstract: This invention is directed to error detection circuitry for combination with data-processing systems The information which comprises the message transmission is transmitted in binary fashion in channels each of a selected number of data bits, and through the addition of two check bits it is possible to detect both single and double parity errors of the asymmetric-type

On the potential function method and the increment error correction rule in pattern classification

Abstract: Based on the basic property that the solution weight vector of the linear pattern classifier can be expressed as a linear function of the training patterns, it is shown that the increment error correction algorithm is a special case of the potential function method. For linearly separable training patterns, a form of potential function which appears to be useful is also proposed.

On a root-distance relation for arithmetic codes,

Abstract: : It is shown that, for all practical purposes, one can synthesize codes of given length and minimum distance by a simple root-distance relation. This gives the strong relation between the arithmetic code and the BCH code.

An Application of Cyclic Coding to Message Identification

Abstract: In certain digital communication systems data is coded into cyclic code words for error correction or detection. To safeguard certain aspects of the system, all the code words of a message may have the same identifying pattern in a group of digits. This increases the redundancy of the message. This paper proposes a method of doing this using little or no redundancy. The message identification (MI) would be contained in a code syndrome which is added to each code word (except the first) of the message. These syndromes are ones that are unused for error correction by the cyclic code. Simple decoding procedures can determine if code words of different messages have been interchanged in certain parts of the system. Random and burst error correction codes are examined to determine suitable syndromes.

Inversion-tolerant random error correcting digital data transmission system

Abstract: A digital data transmission system is disclosed which decodes received error correction coded digital signals properly, irrespective of whether or not the polarities of these signals have become inverted during transmission or reception. The system thus permits a 180* phase ambiguity in the reinsertion of a regenerated suppressed carrier or subcarrier signal in the receiver, thereby simplifying the receiver in addition to correcting errors to improve the reliability of data transmission. The disclosed decoder circuitry includes a plurality of modulo 2 adder circuits for generating a plurality of estimators each of which is the mod 2 sum of an even number of the received digits. These estimators are fed to a threshold decision circuit which provides a serial readout of the decoded digits. The threshold decision circuit may consist of a simple majority decision circuit or a multiple input threshold circuit with either equal or unequal weighting factors on its input estimators.

Data transmission systems

Abstract: 1,169,687. Error detection and correction; error detection and correction. INTERNATIONAL BUSINESS MACHINES CORP. 10 Sept., 1968, No. 42906/68. Headings G4A and G4C. In a data transmission system, a word includes M groups of data and check digits each digit belonging to a unique configuration of groups and each group satisfying the same logical operation, successive shifts of a shifter producing different groups in sequence at predetermined digit locations of the shifter which are connected to logic means to perform the logical operation, the success or failure of the logical operation for each group being recorded in a result register. As described, a 7-bit word having data bits at positions 3, 5, 6, 7 and even parity check bits for respective groups at positions 1, 2, 4 is inserted into the shifter which is shifted in the pattern (calling the shifter stages A, B . . . G) A to D, B to A, C to E, D to B, E to F, F to C, G to G, three times. Before each shift a parity check is performed on stages D, E, F, G and the results (in the result register) are finally decoded to identify the erroneous bit (if any) which is then corrected during read-out of the shifter. The arrangement can be used for producing the check bits from the data bits to construct the word in the first place. Use in computers and storage is mentioned. Ternary and hexadecimal digits are also mentioned. Instead of correction, error detection may cause retransmission or tagging the word bad.

Error Correction in Batch-Fabricated Memories

Abstract: Error correcting codes can be used in memories to produce perfect storage modules from components with some defects. The calculations indicate that the additional complexity of using these codes may be very profitable in increasing the yields of integrated circuit memory arrays.