Showing papers on "Error detection and correction published in 1973"

Error Correcting Properties of Redundant Residue Number Systems

Abstract: The error correcting properties of the redundant residue number systems (RNS) are investigated through a more natural a approach than was previously known. The necessary and sufficient condition for the correction of a given error affecting a single residue digit of any legitimate number in an RRNS is determined. The minimal redundancy allowing the correction of the whole class of the single residue digit errors is derived and an efficienit procedure for error correction is given. Moreover, it is shown that a smaller redundancy and a single redundant modulus may allow the correction of certain important subclasses of single residue digit errors, e.g., the set of errors affecting a single bit in the code. Examples are given.

Error Correction in Redundant Residue Number Systems

Abstract: Two error-correcting algorithms for redundant residue number systems are presented, one for single residue-error correction and the other for burst residue-error correction. Neither algorithm requires table lookup, and hence their implementation needs a memory space which is much smaller than that required by existing methods. Furthermore, the conditions which the moduli of the redundant residue number systems must satisfy for single residue-error correction are less restrictive than that of existing methods. Comparison of the approach on which these two algorithms are based and that of existing methods is given.

Feedback and practice as variables in error detection and correction

Abstract: Adams' (1971) closed-loop theory has response-produced feedback and practice as determinants of the internal reference that is the learned basis of error detection and correction. Two experiments were conducted on error detection and correction in test of this assumption, using a linear displacement task. Amounts of feedback and practice were variables, and both were found to be effective in error detection and correction. The discussion was mainly in terms of the informativeness of feedback channels and what it means for motor behavior.

Plural channel error correcting apparatus and methods

Abstract: Error correcting apparatus is provided for correcting plural channels in error in a parallel channel information system The information is encoded in a cross-channel direction as well as along the channel length The encoded message after storage or transmission is decoded in the cross-channel direction and error correction provided in the in-channel direction in a given number of indicated channels Orthogonally symmetrical redundancy enhances error correction while tending to minimize hardware Plural independent codes interact to correct the plural channels in error The error correcting capabilities of the codes may be matched, no limitation thereto intended

Variable block length synchronization system

Abstract: Framing or block synchronization of digital information signals grouped in blocks of variable length is provided by preceding each block with a synchronization code word. Each synchronization code word is error correction encoded in accordance with a BCH code to indicate the number of information bits in the following block and, hence, the location of the next succeeding synchronization code word. Since only the synchronization code words are error correction encoded, they can be distinguished from the information bits to obtain synchronization. A synchronization receiver acquires synchronization upon the occurrence of an error-free synchronization code word in the incoming signal. Synchronization is maintained thereafter by utilizing the inherent error correction capability offered by the BCH code to correct up to two errors in each received synchronization code word before decoding it to locate the next synchronization word. If, however, three errors are detected in a received synchronization word, synchronization is assumed to be lost and synchronization is thereafter recovered with the occurrence of a succeeding error-free synchronization code word in the incoming digital signal. Two receiver embodiments are disclosed which perform the above-described operation. The first embodiment is adapted to perform a general type of framing synchronization, while the other embodiment is specifically adapted to provide video synchronization.

Modular distributed error detection and correction apparatus and method

Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1''s and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.

Error correction system

Abstract: An error correction system for correcting received erroneous data transmitted from one site of a data link and detected as being received erroneously at a second site of said data link, said error correction system having at each site an encoder for adding an error detecting code to data, a decoder for detecting the code and inserting an error correct signal in data being transmitted in the reverse direction from said second site upon detection of an error in received data at said second site, said decoder at each site also providing instructions at said site upon detection of the error correct signal to cause error injection as well as retransmission of the same data previously detected as being incorrect, the preferred embodiment also includes an elastic memory which acts as a speed converter for the Time Division Multiplexer input thereto. In addition, the preferred embodiment also includes the capability of injecting errors to refill the elastic memory as well as the capability of sending uncorrected data if the correcting capability of the system is exceeded.

Data storage system with deferred error detection

Abstract: Disclosed is a data transfer mechanism between the data bus of a data processing system and a data store. The data transfer mechanism includes common logic for converting between parity coded data on the data bus and error checking and correcting (ECC) coded data associated with the data store. Parity errors in data for presentation to the data store are detected, and single error correction and double error detection (SEC/DEC) syndrome bits are generated from the original ECC bits when data is to be read from the store and presented to the data bus. Additional circuitry is included to cause a signal indicating a single parity error on the data bus to modify the ECC bits generated for presentation to the data store with the data. On a subsequent read of the data from the data store, the modified ECC bits will produce a set of syndrome bits, specially recognized, to cause the data to be presented to the data bus with the original byte parity error recreated for subsequent detection.

Dual product codes for correction of multiple low-density burst errors

Abstract: In many communication channels noise disturbances occur in the form of low-density bursts. Codes capable of correcting multiple bursts of low density are efficient tools of error control for such channels. One such class of codes is presented ia this paper. This Class of codes can be decoded by simple majority logic. The approach is to use codes which are the duals of product codes whose component codes are majority-logic-decodable cyclic codes.

Reverse cyclic code error correction

Abstract: A method and apparatus is disclosed in which reversible cyclic encoding is used to enable reverse error identification. Encoding and decoding is performed in essentially a conventional manner, except that the coding conforms to a reversible cyclic generator polynomial. In the preferred embodiment, a linear feedback shift register is augmented with logic gates which enables the reversing of syndrome bits for subsequent error identification cycling in the event an error is detected.

Method and apparatus of error detection for variable length words using a polynomial code

Abstract: In the transmission of variable length frames of digital information separated by one or more flag sequences, a block check is generated and appended to the information bits at the transmitter. The block check is generated by Exclusive OR''ing a predetermined non-zero number to the high order information bits and generating (n-k) check digits according to a cyclic error detecting code. The (n-k) check digits are Exclusive OR''d with an (n-k) bit non-zero number to produce the block check. At the receiver, the first mentioned non-zero number is added to the high order information bits and an (n-k) digit number is generated according to the same cyclic error detecting code used at the transmitter. This number is checked to see if it conforms to a predetermined number indicating error-free transmission. Utilizing the above approach, transmission errors in or near the flag sequence are detected, as well as those which may occur in the information field.

Lookaside Techniques for Minimum Circuit Memory Translators

Abstract: This paper demonstrates two improvements in coding techniques that could be used for memory word coding. First, within the fixed structure of a Hamming single-error-correcting, double-error-detecting (SEC/DED) code, an improvement can be obtained in circuit cost and operational speed over more conventional code implementations. Second, the mechanics of error correction in a fault-tolerant computer may be carried out via conventional hardware means or by use of the existing system facilities, such as the combination of the microprogram unit, local store, and the arithmetic-logic unit. These improvements may be obtained by the use of Rotational Coding schemes in conjunction with a technique calied "lookaside correction." This paper first shows a generalized algorithm for specifying the parity check matrix of Rotational Codes. The structure implemented by the parity check matrix in this paper is not merely encoding and decoding circuitry, but translates between Rotational Code forms and byte-parity encoded forms. The unique feature of these translators is that use of the Rotational Code permits the error correction to be performed on only a subset of the data word bits, and only if a single-error condition has been detected. The correction mechanism may be either a hardware logic circuit or firmware. The paper concludes with a comparison of the circuit requirements and correctional speed of the Hamming (72, 64) single-error-correcting, double-error-detecting code, as it normally would be implemented, and a Rotational Code translator also operating on 64 data bits and 8 check bits.

Data retrieval and error detection circuitry for a width-modulated bar-code scanning apparatus

Abstract: An apparatus for processing the signals that are generated when a width-modulated bar code is manually scanned includes a simplified serial arithmetic unit and an error-detection circuit which detects errors in scanning technique as well as parity errors and the like. Substantially less expensive to construct than prior arrangements, the apparatus is able to measure the spacing between adjacent bar-coded characters and reject any data if the character spacing is greater or less than is proper at any given point in a data scan. It thus becomes difficult for an erroneous scan to result when a scanning motion reverses itself, begins in the middle of a bar code, or extends over two independent bar codes.

Evaluation of Burst Error Correcting Codes Using a Simple Partitioned Markov Chain Model

Abstract: The simple partitioned Markov chain model is used to evaluate the effectiveness of burst error correcting codes. A Massey diffuse convolutional code is analyzed as an example to illustrate the method. Calculated results and simulation results are presented.

Encoding apparatus having an improved code permitting error reading and error detection

Abstract: An improved encoding arrangement which permits error free reading of a coded index carrier and detection of any errors in such readings in which the index carrier is coded in such a manner that the difference between any code and its inverse is equal to a constant. Means are shown for taking a direct and inverse reading from the index carrier and comparing their difference with a constant to ensure that the encoding system is operating properly.

Analog to digital conversion by subranging with multiple level redundant error correction

Abstract: An analog to digital converter apparatus utilizing subranging with multiple level redundant error correction to increase the speed of conversion. The multiple level correction technique provides a more rapid acquisition of the subrange word.

Bandwidth Compaction Codes for Communications

Abstract: The familiar error-correction codes allow a reduction in the required signal-to-noise ratio at the expense of an increase in bandwidth. Here we reverse the problem and investigate codes that permit a reduced bandwidth at the expense of an increase in the required signal-to-noise ratio. Theoretical properties of these bandwidth compaction codes have been published previously. This paper emphasizes the tradeoff between bandwidth and signal-to-noise ratio when the codes are used. The inherent error detection and error correction properties of the codes are also explored.

Binary counter with error detection and transient error correction

Abstract: This specification discloses a binary counter with two channels each consisting of a binary counter with ripple carry. Both channels store the same binary number, and to advance the count, a pulse is first applied to the input to one counter and thereafter applied to the input of the other counter. The output of each stage in one counter is Exclusive Ored with the output of the same stage in the other counter. The results of this Exclusive ORing is analyzed with additional logic circuitry to determine if the counts in the two channels are or are not equal. If they are not equal the analysis determines which of the counters contains the higher count, and if the difference in the counts is greater than one. This information is then used to find which of the channels is in error and whether the error is a transient error or an error resulting from a hard failure in one of the channels.

Error Reporting, Error Treatment, and Error Correction in Algol Translation — Part 1

Abstract: A number of tasks of a compi ler can be distinguished: to check whether the source program is correct if it is not correct, to give all useful information for correcting it (treatment of statical errors) if it is correct, to translate the program into an equivalent objectcode program to cause the object program to be executed to report any errors occurring during execution (treatment of dynamical errors) In this note some pragmatic observations are given concerning the error treatment in, especially, ALGOL compilers.

Error detector for low disparity code signals

Abstract: This relates to error detection in a PCM system employing a low disparity code. A low disparity code is that type of code that over a long period of time the average number of MARKS and SPACES are approximately equal. When such a code is error free no direct current component is produced, but when an error occurs a low frequency component is introduced into the average signal value. According to the present invention errors in a low disparity code signal are detected by employing a low pass filter that will respond to the low frequency component of the average signal value.

Construction of block error-detection and correction codes to any base

Abstract: A method is given for constructing polynomial error-detection and correction codes to any base using the factorisation of the base into powers of its prime factors. A simple example of a (6, 3) true-decimal single-error-correcting code is given.

Serial transfer error detection logic

Abstract: In a serial transfer channel, a single failing component may cause an even multiple of bit errors to occur in a message. By generating a parity bit for the overall parity of the contents of the transfer register, during information transfer, and using this overall parity bit to check the overall parity of the receive register, all error occurrences resulting from the failing component, including even multiple errors, are detected. Another embodiment detects all errors introduced during transfer of information to or from the transmission line by generating, at the receiving end and/or at the sending end, an intermediate parity bit for all information bits transferred from the transmission line to the receiving register and/or from the sending register to the transmission line.

Speed correction system for a video disk playback system

Abstract: In a video disc system for recovering recorded signals from a video disc by a stylus by establishing relative motion between the disc and the stylus, a speed correction system is provided. A low frequency error correction system is employed to maintain the average speed of the disc at a predetermined speed. A high frequency error correction system is used to compensate for the deviation of the instantaneous relative speed between the disc and the stylus from the average speed of the disc. Means responsive to the presence of recorded signals in the output of the stylus are provided for enabling the low frequency error correction system. Means are provided for delaying the operation of the high frequency error correction system relative to enabling of the low frequency error correction system, permitting stabilization of the high frequency error correction system response and adjustment of the average speed of the disc to the predetermined speed, to precede operation of the high frequency error correction system.

Error correction by redundant pulse powered circuits

Abstract: A redundant circuit which utilizes pulsed power techniques to achieve low power and high reliability by automatic error correction, through the interconnection of capacitors of the various redundant circuit elements.

Transmission strategy and optimal block size in high-speed data communication

Abstract: The problem of transmission of data along communication channels at rates of the order of 107 bits/s is considered. The transmission strategy is discussed and the advantages of data blocking with error detection are indicated. Under this strategy, detailed analysis is given of the time lost in data transmission, in which the presence of optimum values of the block size are revealed. Examples of typical distributions of optimum block size are given as a function of several parameters of interest; the question of channel efficiency is also discussed.

Error detection and correction apparatus for use in a magnetic tape system

Abstract: A deskewing buffer system includes a plurality of storage registers, each of which include a plurality of storage devices. Pairs of storage devices of each register provide storage for a single information channel. The devices of each channel include circuits for detecting when the information bits of a channel are arriving too early with respect to the other channels indicative of a marginal condition in advance of a failure. When the circuits detect such a condition they operate to switch a storage device to a predetermined state indicating a channel failure. Thereafter, the storage devices of a predetermined one of the pairs of the channel are switched to the same predetermined state during succeeding bit intervals signaling for a correction to be made by other error circuits of the system which normally process transit errors. These circuits couple to a last storage register of the buffer system and are operative to check the deskewed contents of the register and generate a signal indicating the type of correction required. The signal causes the contents of one of the buffer pairs of storage devices of the channel to be stored in an output register. Additionally, the system includes circuits for reliably signaling a channel failure upon the detection of a predetermined number of consecutive transit errors.

Bias estimation error induced by parameter uncertainties

Abstract: The effect of a class of plant parameter uncertainties upon the state vector estimation of a system driven by a deterministic forcing function is considered. For this problem the minimization of mean-square error and the minimization of bias error are opposing goals. The set of noninferior solutions for the optimal control problem whose performance index has components mean-square error and bias error is considered, and evaluated.

Analysis, simulation and realization of an automatic digital wireline equalizer system

Abstract: The problem of rapid automatic equalization of a highly distorting wireline channel is considered. An appropriate training signal received through the channel is processed by a 100-tap transversal filter comprising the equalizer and subsequently compared with a locally available properly synchronized reference signal. Errors between these two signals motivate a steepest descent (SD) controller to iteratively synthesize the equalizer's impulse response which tends to minimize the mean-squared error. Using matrix notation, a deterministic analysis leads to a mathematical block diagram of the equalizer system. A computer-simulated example demonstrates the effectiveness of the process in a specific case. The evolution of the equalizer's impulse response is summarized graphically in a "learning surface". Implementation considerations lead to a nearly optimal but considerably simplified system. Smoothing techniques allow for effective equalization in the presence of white additive noise. Experimental observations support predicted results.

Digital electric information processing system

Abstract: 1336981 Digital computers BURROUGHS CORP 13 Nov 1970 [28 Nov 1969] 54201/70 Headings G4A and G4C The digital data processing system of copending Applications 54199/70 and 54200/70 is described with reference to its free field memory unit wherein operands and data segments can be of any size format. By this a requesting device, e.g. a central processor 10, an input/output module 18, or a memory extension controller 15, can extract or insert fields of data anywhere with the memory, a field being defined as a number of bits whose starting bit position may be anywhere within the memory. There may be up to sixteen memory modules 11 and sixteen requesting units, each memory unit being divided into a number of stacks, each stack having 8192 locations of 288 bits each. 256 bits are used for memory space and 32 bits for error coding making up four 72 bit words. Each memory module 11 has a field isolation unit 13 (Fig. 7, not shown) having a 144 bit fetch register which holds two 72 bit memory words, the first word being a copy of a memory word holding the present starting bit of a field and the second word being a copy of the memory word adjacent to the first word if the field is so long that it overflows from the first word. A requesting unit sends a memory control word to the unit 13, the word containing the absolute address of the starting bit of the field and the length of the field, and the address is used to access the two words. A shift register is used to position the words so that the starting position of the field is accessible, a buffer is provided together with parity checking for incoming and outgoing data, and an error register stores data on all other failures. Should the field length extend over more than two words then the next pair of adjacent words are accessed to accommodate the remaining field bits. Should a selected field overlap two memory storage units or modules then the requesting unit will have to generate a fresh memory control word. Provision for one bit error correction is mentioned, data transfer between the various units of Fig. 1, is in parallel and a priority circuit (Fig. 10, not shown) is provided to determine which requesting unit shall have access to one memory module.