Showing papers on "Error detection and correction published in 1975"

Improving Automatic Repeat-Request (ARQ) Performance on Satellite Channels Under High Error Rate Conditions

Abstract: Large round trip delay associated with satellite channels reduces the throughput for automatic repeat-request (ARQ) system of error control rather drastically under high error rate conditians. Ground segments that usually accompany satellite circuits at both ends introduce bursts of errors, during which block error rates tend to be quite high, bringing down the throughput to very low values. In this paper, some schemes that modify the currently known variations of ARQ (Stop-and-Wait and continuous systems) are suggested with a view to obtaining higher throughput under high block error rate conditions. Specifically, the modified Go-Back- N system appears to be quite attractive, as it gives substantial improvement with little additional complexity in system implementation.

Detection of Unidirectional Multiple Errors Using Low-Cost Arithmetic Codes

Abstract: We show that a low-cost arithmtetic code with group length n detects all unidirectional multiple errors that affect fewer than n bits, as well as a larger class of such errors confined to a restricted set of bit positions.

Performance of Hybrid Error Control Schemes of Satellite Channels

Abstract: The effectiveness of hybrid error control schemes involving forward error correction (FEC) and automatic repeat request (ARQ) is examined for satellite channels. The principal features of the channel are: large round-trip transmission delay due to the satellite link, and burst errors introduced by the terrestrial links that connect the users to the satellite link. The performance is estimated for two channels described by Fritchman's simple partitioned finite-state Markov model, and is compared to that obtainable if the channel is considered as a binary symmetric channel of the same bit error probability. Results show that the hybrid schemes offer substantial improvement over ARQ and FEC, and that an optimum exists for the number of errors corrected to obtain maximum throughput efficiency.

Redundancy system for data communications

Abstract: A redundancy system for data communications upon two duplicate communication channels, each having transmission and reception circuits, characterized by a switching circuit for selecting one of said two communication channels, a single error detection circuit for detecting an error in the signal transmitted, and a control circuit for the switching circuit arranged to cause said two communication channels to alternately transmit signals when both the channels are in normal operation, and to cause one of said two channels to be selected when the other fails. The two channels share the error detection circuit and the control circuit and can therefore be built at a reduced cost and operated efficiently. Since the two channels are regularly checked for errors, they are operated with increased reliability.

On the minimal redundancy of binary error-correcting codes

Abstract: This paper obtains new lower bounds for the redundancy of both arbitrary and constant-weight binary codes with a fixed error-correcting capability.

Reliability Analysis of Systems with Concurrent Error Detection

Abstract: There is an increasing use of error detectors and correctors in computer subsystems, such as parity detectors in memory modules and residue checkers in arithmetic units. Their fault tolerant characteristics are studied through the model of detector redundant systems. Their reliabilities and availabilities are analyzed and compared with those which do not have any such error detectors. The design of fault isolating and reconfiguring networks used in the implementation of such systems are developed.

Method and apparatus for in-band signalling in data transmission

Abstract: An in-band signalling system for the transmission of both data and control signals through a common communications channel is disclosed. Unique means of distinguishing data bits from control bits is employed without the use of additional bandwidth over that which would be required for the data alone. A novel method for signalling includes the steps of translating the data bits into a different code set than the original, examining it for control words and if any are present, modifying or corrupting the data and thereafter combining on a time division basis the translated and/or modified data and control words over a transmission channel. To receive, data is inversely modified and control words detected. Error detection of control words is achieved by translating control words followed by their complements.

Development of a transmission error model and an error control model

Abstract: : The objective of this study is to choose an error detecting code for use in general purpose digital communication networks which employ automatic repeat request. To choose a code it is necessary to characterize the channels used by the communication network.

Error detection/correction system

Abstract: In the automatic processing of documents having bar encoded printing thereon, selectively variable error detection and correction codes are added to a bar encoded data field. Read errors which may occur from the reading of document data fields having overprints of inks of various types, colors and densities thereby may be substantially reduced. More particularly, either, neither or both a random parity code and a Bose-Chaudhuri-Hocquenghem (BCH) code may be added to a data message for a bar code printing to accommodate error correction and detection systems having differing processing capabilities. Further, the BCH code may be dynamically and selectively altered to accommodate both documents and data fields of varying lengths.

Enhanced error correction

Abstract: Multiple symbol correction employing auxiliary pointers is enhanced by unique interaction of code structures either with ambiguous auxiliary pointers or data structures for precisely locating errors. For example, a code apparatus can correct two symbols in error only with two error location pointers; with three error location pointers, the code cannot correct the errors since error location is ambiguous. Once this has been determined, the features set forth in the present invention are employed to delimit the error burst such that the code apparatus may correct two symbols in error, even with ambiguous error location pointers. With no auxiliary pointers, methods and apparatus can create such auxiliary pointers in particular data structures and error patterns.

Automatic time-base error correction system

Abstract: An automatic time-base error correction system having a pair of random access memories, in which an input signal including timing errors is written in one of the random access memories alternatively at a rate corresponding to the timing errors, and an output signal is alternatively read out from the memories at the constant rate.

Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement

Abstract: When errors occur which exceed the correction capability of an error correcting code, the only recourse to restore the original memory function is to physically replace the failed entity. In this paper the authors propose an automatic reconfiguration technique which uses the concept of address skewing to disperse such multiple errors into correctable errors. No additional redundancy other than that required for the error correcting code is needed. The skewing mechanism is derived using the theory of orthogonal Latin squares.

On forward error correction with adaptive decoding (Corresp.)

Abstract: A method is proposed that utilizes punctured Reed-Solomon (RS) block codes for adaptive coding. Part of the redundancy of the RS codewords is used in a convolutional coding framework. This enables some codewords to use more redundancy for correcting errors, while other adjacent codewords use less redundancy.

Feedback Decoding of Convolutional Codes

Abstract: Publisher Summary In recent years, convolutional coding-decoding techniques have become increasingly popular in digital communication systems where there is a requirement to provide error correction and to improve communication efficiency This chapter focuses on the feedback decoding of the convolutional codes Convolutional encoding with feedback decoding is capable of providing error correction performance superior to that of block codes for the same level of equipment complexity Convolutional encoding-decoding is more desirable than competing block encoding-decoding techniques in most of these applications because, for a given error correction capability or improvement in communication efficiency, the systems based on convolutional codes are less complex and hence less costly This has been shown theoretically and in practical equipment designs and implementations In general, feedback decoder implementations have the added attraction that they can be made effective on burst error channels Interleaving of data in the encoder and deinterleaving in the decoder can be performed in a straightforward manner, effectively breaking up error bursts and making the channel appear memory less to the decoder Feedback decoders are simple to implement Feedback decoding is especially attractive on burst error channels as very effective interleaving, to break up long bursts, can be implemented simply with no increase in code synchronization requirement

Means and method for error detection and correction of digital data

Abstract: Apparatus for detecting and correcting errors in one or two tracks of a multi-bit, multi-track data group which includes an error correction character (ECC). The received data group is simultaneously stored and applied to an ECC generator which operates upon each data byte according to an operator B such that an error correction character ECC is reproduced. The ECC is of such a nature that another application of operator B produces a new character termed an error vector E. If all of the received data characters are correct all data bits of the error vector E will be zero. The error vector may be regressively operated on by the operator B and sequentially compared to a locally-generated parity vector P n . If single track is in error its identity is determined by the number of cycles by operator B necessary to obtain an error vector identical to the parity vector. If more than one track is in error, and identified by means of pointers, the tracks and the difference therebetween are identified and a divisor generated to operate on the previously-obtained combination of error and parity vectors. The resulting dividend comprises an error vector for a least significant track, and is applied through a correction matrix to correct that track. The least significant track error vector is also combined with locally-generated parity to produce an error correction vector for the most significant track, which is applied to a correction matrix to invert erroneous bits of data in the relevant track of uncorrected information received from the storage register.

Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection

Abstract: A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.

One-error correction convolutional coding system

Abstract: A rate one-half random error convolutional coding system corrects the theoretical limit of one error out of four successive bits An information bit stream is processed through the system encoder which is comprised of a two-bit shift register and a modulo-2 adder The encoder generates a parity bit formed by the modulo-2 summing of successive pairs of information bits, and produces a convolved transmission bit stream The system decoder is the replica of the encoder in combination with a two-bit syndrome register, an AND gate, complementary feedback circuitry, and an output modulo-2 adder Overall system performance is the simplest, fastest, and highest performing of all such systems known to date

One-step majority-logic decoding with symbol reliability information (Corresp.)

Abstract: A method of using reliability information in one-step majority-logic decoders is presented. The idea is, basically, that the received binary digits are corrected in an order such that the least reliable digit is first corrected. With this method the error correction capability of the decoder is extended for large signal-to-noise ratios (SNR's). Different decoding algorithms are used when the number of orthogonal parity-check sums are even and odd, respectively. Computer simulations are presented for some short codes with binary antipodal signals on the additive white Gaussian noise channel.

Code error detecting system in digital code transmission

Abstract: A code error detection system in a digital phase modulation communication system comprises on the transmitter side a first code train generator for generating a pseudo-random code train and a second code train generator for generating codes which are complementary to each other at n-bit intervals. A 4-phase phase modulator is driven by another code representative of the exclusive OR function of the pseudo-random and complementary codes.

Error-correctible bit-organized RAM system

Abstract: A memory organization system is disclosed which comprises an improved, bit-organized RAM system. The invention substantially limits errors within the RAM system such that they are error-correctible by existing error detection and correction means. Commonly available RAMs are organized on a logic board such that each bit of a word being addressed is provided by a different RAM chip and is driven by a distinct driver. In this manner a malfunction in either a chip or a driver circuit results in only a one-bit error per word and overall system performance is also improved.

Error correction system

Abstract: PURPOSE: To increase an error correction function by means of a simple structure including a plurality of multiple error correction codes. COPYRIGHT: (C)1976,JPO&Japio

Automatic error correction system for data processor - executes each programme sequence twice and compares results

Abstract: The error detection and correction system for programme errors in a data processor, has each programme sequence executed twice, with a significant code used to represent the result of each sequence execution. These codes are compared and the next programme sequence is requested when the codes are in agreement. The programme sequence is recalled when the codes vary from each other, with the programme sequence data and the corresponding addresses being stored. Pref. a storage register (A, B, C) has a memory zone for the sequence data and the addresses and a register for storing the code word signifying the result.

Data transmission with variable-redundancy error control over a high-frequency channel

Abstract: Results of computations and field tests on a binary-data-transmission system, operating at 1 kbaud over an h.f. channel, are presented. Error correction is effected by means of error detection and automatic request for repeat, via a feedback channel (a Post Office private line). A set of short, fixed-block-length cyclic codes is available, a code of appropriate redundancy being automatically selected to match the varying channel conditions. The decision about which code to use is made at the receiver, and the transmitter is informed via the feedback channel. The results show that relatively simple, reliable, and efficient data communication can be realised by this means.

Structure and error detection in computer software

Abstract: : A model of the error detection process for the testing of software has been developed to investigate the relationship of computer program structure to error detection and test effort. The model has been implemented as a simulation. Analytical results have also been obtained. (Author)

Systematic Construction of Cyclically Permutable Code Words

Abstract: A numerical procedure for determining the cyclically permutable code of any length over an arbitrary alphabet is outlined. This method is easily programmed on a digital computer. A formula for the Hamming weight distribution of the code is also given. The results for the 12 bit binary cyclically permutable code are presented along with the weight distribution of the binary codes through length 14.

Evaluation of 32 Degree Polynomials in Error Detection on the SATIN IV AUTOVON Error Patterns.

Abstract: : An examination of the capabilities of certain 32 degree polynomials to detect errors on the SATIN IV real channel measured AUTOVON error patterns has been made. It is demonstrated that while some polynomials considered will detect all error bursts in the data, others will leave significant number of undetected errors. Thus, while a 32 degree polynomial is sufficient (on the data sample) for 100% error detection, it must be chosen carefully. (Author)