Showing papers on "Error detection and correction published in 1976"

Error Control Coding Handbook

Abstract: : With the continued improvement in coding techniques and the implementation of these techniques, and the growing acceptance of error control coding, increasingly many systems engineers are incorporating error control codes into communication systems. However, due to the rapid changes in this field and the fact that much of the information needed to decide whether error control coding should be used is in widely scattered or unpublished sources, it has been difficult for the systems engineer to weigh the advantages versus the costs of various coding systems and to specify the parameters of a coding system when error control coding is selected. The purpose of this report is to provide a reference which can be used by systems engineers to aid in selecting and specifying error control codes.

Digital communications receiver for dual input signal

Abstract: A dual channel receiver system for receiving polarized signals, which system reduces cross-interference between the signal channels by utilizing adaptive filter equalization means responsive to the input received signals and to error control signals for providing a plurality of weighting signals which are used to combine selectively with the input received signals to reduce the errors, including particularly cross-polarization and noise errors therein. The channels each include decision-directed error signal generating means for providing such error control signals. The system also includes means for preventing system failures wherein both received signals fade simultaneously under which conditions data reversal in the channels could occur and wherein one received signal fades under which condition the same data is produced in both channels.

Spatial diversity satellite communications system with error control

Abstract: A spatial diversity satellite communications system adapted to provide its own error control. The diversity communications system utilizes transmitting station selection or burst switching in the up-link and both probabalistic and algebraic error control in the down link to increase message accuracy and to overcome precipitation attenuation. Specialized multiple level decision demodulators are employed to exploit the inherent redundancy supplied by having available multiple signals embodying identical messages. Information is fedback, once the system is operating, and is used to select the optimum transmitter site. However, all available receivers are utilized and the received messages are statistically evaluated to accurately reproduce the received message.

Implementation of an Experimental Fault-Tolerant Memory System

Abstract: The experimental fault-tolerant memory system described in this paper has been designed to enable the modular addition of spares, to validate the theoretical fault-secure and self-testing properties of the translator/corrector, to provide a basis for experiments using the new testing and correction processes for recovery, and to determine the practicality of such systems. The hardware design and implementation are described, together with methods of fault insertion. The hardware/ software interface, including a restricted single error correction/double error detection (SEC/DED) code, is specified. Procedures are carefully described which, 1) test for specified physical faults, 2) ensure that single error corrections are not miscorrections due to triple faults, and 3) enable recovery from double errors.

A Double Track Error-Correction Code for Magnetic Tape

Abstract: An error-correction code, presented here, uses two redundant tracks and one redundant character which are formed from the askew and the vertical redundancy check (AVRC) bits. The error-correction capability of this code is the same as for the ORC Patel and Hong's code, but the encoded codeblock dimension is not subject to constraints.

Hybrid Error Control Using Retransmission and Generalized Burst-Trapping Codes

Abstract: On most real channels hybrid error control schemes are expected to provide a throughput higher than that of automatic repeatrequest (ARQ) systems and a reliability better than forward error correction (FEC) systems. On compound channels, channels with a mixture of random and burst errors, generalized burst-trapping (GBT) codes seem to be quite effective for FEC. In this paper, a hybrid scheme with Go Back N ARQ as the retransmission component and GBT code as the FEC component, is described. Its performance is analyzed in terms of throughput efficiency and undetected error probability and is compared with that of a forward-acting GBT code. Numerical calculations of the parameters are presented to illustrate the performance.

Language Correction Using Probabilistic Grammars

Abstract: Error correction of programming languages has been effected in a heuristic fashion; error correction in the information-theoretic sense is very precise. The missing link is provided through probabilistic grammars. This paper provides the theoretical foundation for the precise construction of an error correcting compiler. The concept of code distance is extended to account for syntax in language. Grammar modifications are demonstrated so that a probabilistic parsing algorithm corrects various kinds of linguistic errors using an ideal observer rule. A generalized error correcting algorithm is described.

Apparatus and method for storing parity encoded data from a plurality of input/output sources

Abstract: Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an addressed location are operative to generate a number of syndrome bits having a predetermined characteristic for indicating the existence of an uncorrectable error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.

Error correcting and controlling system

Abstract: An error correcting and controlling system having syndrome generating means for generating syndromes of data to be checked and memory means for storing error bit positions in which system the syndromes form addressing inputs to the memory so that the error bit position information stored in the address positions corresponding to each syndrome in the memory may be read out and processed for the purposes of error detection and correction. As a result, the check circuits of the present system have been simplified as compared with conventional check circuits.

Error correction circuit utilizing multiple parity bits

Abstract: An arrangement for correcting errors in words read from a memory due to a bit in a word location of the memory being stuck in one of the two binary states, 0 or 1. The arrangement is used in cooperation with parity error detection arrangements which utilize more than one parity bit per word. Upon detection of a single parity failure in a word read from a selected word location in memory the complement of the data word which is indicated to contain a parity failure is placed in the selected word location; the memory is read at the selected word location and the data so obtained is placed back into the selected word location of the memory. After this step the data in the selected word location of memory comprises the complement of the correct data word and the parity bits are all the complement of the correct parity for that data word. The correct data word for use by the processor is thus generated by complementing this later received data. On subsequent reading of the memory at a previously failed location the corrected word in the location is recognized as such by a failure of all of the parity bits. A word in which all of the parity bits fail is automatically complemented and the result is utilized in the data processor.

Check system for detecting malfunction of an error detection circuit

Abstract: In an error detection circuit of a data processing circuit having a parity generator, a parity signal is predicted from an initial value determined by the data storing state of the data processing circuit in its initial state and a count value of the number of logic "1" or "0" in input data of the data processing circuit and/or the number of logic "1" "0" of output data, obtained by counters or the like. A parity signal derived from the parity generator is compared with the predicted parity signal to detect malfunction of the error detection circuit.

Error correction encoder and decoder

Abstract: The present invention relates to an apparatus and method for detecting and correcting burst errors of indeterminate length occurring in data entered along a magnetic tape or other storage medium. An encoder and decoder arrangement is provided wherein parity or check bytes are encoded and decoded across data blocks which are measured along and across the tracks of the storage medium and wherein the parity or check bytes are read onto separate tracks of the storage medium. The present invention provides for the continuous encoding and decoding of data because the parity bytes and data bytes are conveyed to and from the storage medium along separate tracks.

Error correction code and apparatus for the correction of differentially encoded quadrature phase shift keyed data (dqpsk)

Abstract: This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations: P.sub.8.sup.a = i.sub.8.sup.a ⊕i.sub.8.sup.b ⊕i.sub.6.sup.b ⊕i 1 b ⊕i 3 c ⊕i 2 c P.sub.8.sup.b = i.sub.8.sup.a ⊕i.sub.6.sup.a ⊕i.sub.3.sup.a ⊕i 5 b ⊕i 8 c ⊕i 4 c where i 8 a , i 8 b and i 8 c are the three information bits in the set associated with the parity bits P 8 a and P 8 b while the other information bits are from the seven sets of the sequence preceding the set associated with the parity bits.

Art of writing a Runge--Kutta code

Abstract: The problem considered is the solution of u' = f(x,u) for x between a and b with u(a) given. Runge--Kutta methods and when to use them are briefly described. Choice of step size is important. Characteristics of several codes employing Runge--Kutta methods are listed; the characteristics vary. Aspects of the algorithms discussed include error control, step size, external limits, scale of the problem, computer arithmetic, accuracy, and output. Characteristics of the code RFK45 are given. (RWR)

Error detection and correction locator circuits

Abstract: A main memory system includes encoder and decoder circuits. The encoder circuits are connected to receive data bits and parity bits and from them generate check code bits which are stored with the data bits during a write cycle of operation. The decoder circuits are connected to receive data and check bits read out from memory during a read cycle of operation. The decoder circuits include a plurality of decoder circuits and error locator circuits. Circuits via exclusive OR circuits generate a number of syndrome bit signals. These signals are divided into first and second groups. The first group is coded to specify which one of a number of decoder circuits comprising the error locator circuits is to be enabled in the case of an error condition. The second group of signals is coded to designate the particular data bit to be corrected by the decoder circuits. Predetermined output terminals of each of the decoder circuits representative of valid single bit data error conditions are applied to a plurality of correction circuits for modification of the data signals as specified by the decoder circuits. Additionally, signals from predetermined output terminals of certain ones of the decoder circuits representative of certain single check code bit error conditions are utilized for providing the correct parity for the data signals associated therewith.

The effects of error correction treatments upon adequate and accurate communication in the written compositions of adult learners of English as a second language

Abstract: 3. When a map, drawing or chart, etc., was part of the material being photographed the photographer followed a definite method in "sectioning" the material. It is customary to begin photoing at the upper left hand corner of a large sheet and to continue photoing from left to right in equal sections with a small overlap. If-necessary, sectioning is continued again — beginning below the first row and continuing on until complete.

A Class of Soft Decision Error Detectors for the Gaussian Channel

Abstract: The main idea of this concise paper is to use symbol reliability information for improving the performance of error detectors. A class of soft decision error detectors (SDED's) is presented, where low weight error patterns are selectively corrected. The reliability numbers govern which error pattern to correct. Asymptotic performance and bounds are derived for the Gaussian channel. It is shown that singleerror correcting SDED's without thresholds have an exponentially lower repeat request probability than the hard decision error detector, but the same exponent in the probability of undetected errors. Detectors with thresholds are also considered. In this case it is possible to contruct an error detector with both better probability of undetected errors and better probability of repeat request than for the hard decision error detector (HDED). Bounds and computer simulations are presented and SDED's are compared to HDED's.

Error correcting codes for satellite communication channels

Abstract: This paper addresses the problem of efficient forward error correction on differentially encoded, quadriphase-shift-keying (DQPSK) channels. The approach is to design codes to correct the most probable error patterns. First the probability distribution of error patterns is derived. Then a class of convolutional codes that correct any single two-bit error is described. Finally a threshold decodable code that corrects all single, and many double, two-bit errors is presented.

Communication method and apparatus for providing an enhanced signal from diverse signals

Abstract: A communication method and apparatus for providing an enhanced signal from diverse signals whereby high accuracy communication may be established between remote points, even in the presence of severe signal fading and drop outs. The information to be transmitted is provided in digital form and formatted so as to have a Barker code or sync code of adequate length to achieve the desired false alarm rate filtering, followed by the data broken up into data blocks each containing an error detection and correction code for the respective block so that accurate microsecond processing of the signals is possible. The digital signals are modulated and transmitted, ideally with a plurality of frequencies, and are received, preferably at a plurality of remote satellite receiving sites with a plurality of space, path and polarization diversity techniques. The received signals are then processed and a data output signal is constructed from the multiple signals by utilizing the data blocks for which the sync code was properly received and for which the respective error detection and correction code indicates is true data.

Pulse compression recording

Abstract: Small media defects are a major limitation to data reliability at high magnetic recording densities. One way of overcoming this limitation is to use an error correction code. In this paper, Pulse-Compression Recording (PCR) is proposed as a method in which the energy of each data bit is spatially dispersed in such a manner that the recorded information is insensitive to small media defects or short bursts of noise.

Improving the Throughput of an ARQ Stop and Wait Scheme for Burst Noise Channels

Abstract: The repeat request codeword in an ARQ data transmission can be the detected error syndrome. In that case, there exists an optimal single-burst detecting scheme which improves the throughput of a Stop and Wait scheme, especially under high error rate conditions.

Error detection in data base systems

Abstract: Incorrect data poses a serious impediment to the effective use of computerized data bases. Conventional approaches to the design and implementation of automated data error detection systems are inadequate for large and complex data bases. Partly, this derives from the inherent intricacy of the problem, with decisions being required as to what checks to perform, how and when to do the checking, and how to respond should an error be found; writing procedures to accomplish these functions is a difficult programming task. Also at fault is the unrealistic and overly simplistic view of data correctness embodied in most contemporary systems."Intelligent" data checking systems are required, which possess more extensive knowledge of the data base environment. They will need to understand the structure of the world which the data base models; the way the data base is used, and the relative importance of its various components; the sources of the errors that might occur and the costs of detecting them; and the patterns and rates of errors that actually do occur. Such a system would then be in a position to detect a wide range of errors, allocating its resources in a systematic fashion and responding appropriately to different error situations.

A simple description of an error-correcting code for high-density magnetic tape

Abstract: Hong and Patel have described an efficient error-correcting code for magnetic tape, which has been successfully used on the IBM 6250 bits-per-inch nine-track magnetic tape units. This paper gives a simple description of the code, without using Galois fields.

Techniques for Correcting Transmission Errors in Video Adaptive Delta Modulation Channels

Abstract: We investigated the effects of channel errors on an adaptive delta modulator used to encode video signals. The investigation revealed that channel errors caused a permanent shift in the dc level of the delta modulator's estimate. Errors in the step size, on the other hand, were transitory and had no noticeable effect on the received pictures. We then presented three error correction schemes to minimize the visibility of the channel errors in the received picture. The first scheme required the transmitter to periodically send the correct dc level of the estimate to the receiver. The second method employed a leaky integrator, and the third method used line-to-line interpolation.

Automatic Error Correction

Abstract: The automatic detection of errors gives considerable protection against serious errors. With batch processing systems this may be sufficient, since there is ample time available for the manual diagnosis of the error and its eventual elimination. In contrast to this, real-time systems will rarely allow for manual intervention since the time constraints may be very tight. Thus mere error detection is insufficient in such a situation. As was stated in the previous chapter automatic error detection also has a negative influence on reliability. Precautions must therefore be taken with real-time systems to ensure that the system becomes operational again in the shortest possible time — often within a fraction of a second. The new operating level, which is aimed for after an error has occurred, in general will not be able to support all the tasks expected of a fully functional system. This is, however, not critical with the majority of systems, since the requirements for a system are divided into primary functions, which must be fulfilled under all circumstances, and secondary functions, which may be abandoned in the event of the occurrence of an error (see chapter 3). Clearly a system that automatically corrects errors must contain considerably more redundancy than would be required for mere detection. The amount of this additional redundancy determines which error types may be circumvented. While the correction of transient errors requires data and time redundancy as well as software for restarting, correction of permanent errors requires additional hardware components and software modules.

Comments on "Bounds on Probability of Error in Decision Feedback Equalizers"

Abstract: In the above paper1 a technique was proposed to derive an upper bound on the error probability of a decision feedback equalizer. It involves decomposition of the probability density function of residual intersymbol interference and derivation of Chebyshev-type bounds on the error functionals over the decomposed functions. In this correspondence, we demonstrate that the technique is not applicable in general. The result is not a bound in many cases.

System for error control and phasing in interconnected arq-circuits

Abstract: A system for reducing the time for repeating erroneous signals through a series of interconnected ARQ-circuits (automatic error correction circuits), in which the durations of the repetition cycles of the ARQ-circuits, as compared to one another, are not equal. The system comprises means at a connection point and capable of storing a number of signals related to each propagation time of a circuit located before the connection point, when a circuit located behind the connection point goes through a repetition procedure including means for generating a special signal to indicate when a repetition procedure is in process in one of said ARQ interconnected circuits to prevent the other interconnected ARQ circuits from also going through their repetition procedures.

A Double Error-Correction Scheme for Peripheral Systems

Abstract: In multiple digital recording peripheral systems, the errors which are encountered are burst-type errors which may occur in several tracks or channels. This paper discusses methods and implementation procedures for correcting a series of errors or erasures of arbitrary length in any one or two tracks of a multi-channel system. We have shown that such errors in multiple tracks may be detected and corrected using a two-redundant Hamming code over a Galois field mathematical structure in conjunction with error track pointers. The detection/correction scheme considered here can correct N-bit blocks, thereby correcting an error burst of arbitrary length in any single or pair of tracks. The error-correction (EC) scheme is shown to be applicable to two types of data formats or arrays. Additional error detection is provided to check the validity of error correction to enhance reliability above that of double error correction. Implementation methods pertaining to the above EC scheme are discussed. Examples of single and double error corrections for two types of data formats or arrays are included.

Multiple-burst correction techniques for slowly fading channels

Abstract: Slowly fading channels, such as a troposcatter communication link, are characterized by multiple error bursts which may last for many thousand channel digits, as well as by random errors. It is shown that even the best random error-correcting codes cannot be effective on this type of channel unless some time delay between code letters is introduced to reduce the correlation between channel errors within the code. In addition to the conventional approach of interleaving code letters to obtain error independence, two alternative coding approaches are considered which correct random errors as well as detect and correct multiple bursts, i.e., multiple channel fades. A concatenated coding approach, based on interleaving inner code blocks but not interleaving digits within an inner block, and a new multiple-burst correction code based on generalized burst trapping codes, are shown to represent attractive alternatives to the conventional interleaver approach.

Diagnosis circuit for failure detection

Abstract: PURPOSE:A circuit to find out defect in error correction circuit by connecting memory to central processor and using such as diagnosis program