Showing papers on "Error detection and correction published in 1977"

Retransmission Error Control with Memory

Abstract: Automatic-repeat-request (ARQ) is one of the most commonly used error control techniques today. In this paper, an error control technique that is a basic improvement over ARQ is presented. The technique uses the simple idea of utilizing erroneously received blocks in an ARQ system for error control, retaining most of the other aspects of ARQ. The technique is termed ARQ-with-memory (MRQ). The general MRQ system is described, and simple upper and lower bounds are derived on the throughput achievable by MRQ. The performance of MRQ with respect to throughput, message delay and probability of error is compared to that of ARQ by simulating both systems using error data from a VHF satellite channel being operated in the ALOHA packet broadcasting mode [9].

Performance characteristics of rules for internal quality control: probabilities for false rejection and error detection.

Abstract: When assessing the performance of an internal quality control system, it is useful to determine the probability for false rejections (pfr) and the probability for error detection (ped). These performance characteristics are estimated here by use of a computer stimulation procedure. The control rules studied include those commonly employed with Shewhart-type control charts, a cumulative sum rule, and rules applicable when a series of control measurements are treated as a single control observation. The error situations studied include an increase in random error, a systematic shift, a systematic drift, and mixtures of these. The probability for error detection is very dependent on the number of control observations and the choice of control rules. No one rule is best for detecting all errors, thus combinations of rules are desirable. Some appropriate combinations are suggested and their performance characteristics are presented.

Joint Source and Channel Coding

Abstract: : The advantages and disadvantages of combining the functions of source coding ('data compression') and channel coding ('error correction') into a single coding unit are considered. Particular attention is given to linear encoders, both for sources and for channels, because their ease of implementation makes their use desirable in practice. It is shown that, without loss of optimality, a joint source/channel linear encoder may be used when the goal is the distortionless reproduction of the source at the destination. On the other hand, it is shown that in general there is an inherent and significant loss of optimality if a joint source/channel linear encoder is used when the goal is relaxed to reproduction of the source within some specified non-negligible distortion. (Author)

Correcting human error in alphanumeric terminal input

Abstract: An automatic method for correcting spelling and typing errors from teletypewriter keyboard input is proposed. The computerized correcting process is presented as a heuristic tree search. The correct spellings are stored character-by-character in a psuedo-binary tree. The search examines a small subset of the database (selected branches of the tree) while checking for insertion, substitution, deletion and transposition errors. The correction procedure utilizes the inherent redundancy of natural language. Multiple errors can be handled if at least two correct characters appear between errors. Test results indicate that this approach has the highest error correction accuracy to date.

High speed double error correction plus triple error detection system

Abstract: A single and double error correction and triple detection system using cyclical redundancy codes based on the generator polynomials: G(1171) = X.sup.9 + X.sup.6 + X.sup.5 + X.sup.4 + X.sup.3 + 1 g(1513) = x.sup.9 + x.sup.8 + x.sup.6 + x.sup.3 + x + 1.

Error correction for signals employing the modified duobinary code

Abstract: Single errors can be detected and corrected in a signal employing a 3-level modified duobinary code. Error correction is predicated on the concept of maximum likelihood of error for the bit having the maximum departure from normal amplitude (error differential). A converter accepts the modified duobinary signal, decodes the signal to obtain a binary output signal and determines the error differential for each bit. Bits of the binary output signals are temporarily stored in a sequential storage device. The error differential is applied to an input of an error analyzer. An error detector determines if an error has occurred during an error correction interval which interval is established by successive extreme levels of the modified duobinary signal. The error analyzer tracks the location of the bit having the largest error differential during each error correction interval. A plurality of bit correctors, one for each time slot of the sequential storage device, operate in combination with the error detector and the error analyzer to alter the bit having the highest error differential following detection of an error.

Signal transmission system with an error control technique

Abstract: A signal transmission system embodying this invention which can control errors comprises a selective automatic repeat request (ARQ) system for controlling errors occurring in transmission of data on telephone data communication channels. With this selective ARQ system, an error-controlling signal conducted through a backward channel does not contain a check bit for detection or correction of errors, thereby preventing a time loss which might occur if a error-control signal was repeatedly issued between the transmission and receiving sides. The subject signal-transmitting apparatus is adapted to be used in a static image transmission having a large amount of data and has such a circuit arrangement as attains the efficient transmission of data and the display of an error-free image of good picture quality.

Parallel-processing error correction system

Abstract: A parallel-processing error correction system for digital data transmission employing a code-polynomial division circuit having a serial-type shift register for a cyclic code. Provided with null input lines, one for each data input line, a set of switches for selection between the data and null input lines, and another set of switches associated with buffer registers for series connection therebetween, the device can be readily adapted for any change in number of parallel input bits by switch operation.

Method and apparatus to permit substantial cancellation of interference between a received first and second signal

Abstract: The present invention relates to method and apparatus for substantially reducing the effects of interference at a receiver between concurrently received first and second digital signals which use the same frequency spectrum. Interference between signals is effectively reduced by transmitting the first digital signal in an uncoded form while concurrently transmitting the second digital signal with both reduced capacity when compared with the first signal and in coded form using a forward error correcting code such as, for example, a block or convolutional code. At the receiver intercepting both digital signals, a suitable detection process is performed to decode the second signal and separate both signals. The present invention is applicable to the simultaneous satellite transmission of an area coverage beam and a plurality of spot coverage beams or to increase capacity on a radio channel.

Offset correction circuit for phase detectors

Abstract: An offset error correction circuit for improved reception of signals by compensating for any offset error voltage produced by a phase detector in the absence of an input signal to the detector. The error correction circuit translates the offset error voltage into a digital value and stores that value in a counter. When a PSK signal is applied to the circuit, the error correction circuit subtracts the stored value of the offset error voltage from the output of the phase detector which compensates for the offset error. The compensation for the offset error provides an improved signal to noise ratio.

Differential detection systems with non-redundant error correction

Abstract: The differential detection system comprises a demodulator for a modulated carrier transmission system for binary signals, in which a symbol detected from the phase difference between the received signal delayed by one signaling interval and the signal received in the present signaling interval is converted into data and a symbol detected from the phase difference between the received signal delayed by two signaling intervals and a signal received in the present signaling interval is converted into parity. The data and the parity are applied to a decoder for a rate 1/2 single error correcting self-orthogonal convolutional code effecting demodulation with non-redundant error correction. The correction system is also applicable to demodulate a carrier wave modulated by m (an integer) level digital data.

Electronic time base error correction methods and arrangements

Abstract: OF THE DISCLOSURE: An electronic time base error correction technique in which the color video signal is recorded so that in playback in at least one channel sync information is provided along with the luminance information and the color burst information along with the chrominance information. Feed-back loops are provided to derive from the sync information coarse-correction of the video signal and derive from the burst information fine-correction of the video signal. The color burst extends over the entire blanking interval. Three different approaches are specifically disclosed: in the first, coarse- and fine-correction are carried out in tow tandem connected stages, respectively. In the second, coarse-and fine-correction are accomplished in the same stage by means of a bi-level phase comparator. The third approach is a modification of the second approach, in which the first and second techniques have been combined.

Method and apparatus for error correction

Abstract: In a device in which an independent variable is stepped or scanned between a first limit and second limit and in which device there is an error which is a function of the independent variable, error correction is obtained by storing correction values, preferably of an incremental nature, for each of a plurality of steps of the independent variable, establishing a location marker which can be identified as different from the error correction data, moving the location marker so as to always be adjacent the error correction for the current position or step of the independent variable and reading out the error correction at the point of the location marker.

Partial correction of transmission errors in d.p.c.m. without recourse to error correction coding

Abstract: A method for partially correcting transmission errors in a 1st-order d.p.c.m. system, without recourse to channel coding, is described. A simple detection algorithm based on the statistical properties of a sequence of differences between adjacent samples of a modified decoded sequence is used to identify the erroneous samples. Three different correcting algorithms are described. Substantial improvements in the decoded waveform are achieved, and, for a Markov input process, an error rate of 0.04% in the first and second most significant digits, an improvement in s.n.r. of 7dB is achieved.

Decoder for error-correcting code data

Abstract: An error correcting decoder is disclosed which blocks correction of bits received during periods of relatively high signal intensity levels. A syndrome register and decision circuit provide error correcting bits for all bits which the sequence of input data determines to be in error. But only those data bits which occur during low levels of signal intensity are corrected.

Error correction system by means of numerical control

Abstract: PURPOSE:Error correction system capable of achieving position control, a single stroke and extremely accurately, of pitch error and backlash quantity as one whole but not as separate.

A new method for error correction in strings with applications to spoken word recognition

Abstract: This work focuses on the problem of error-correction in strings. We propose a new method for correcting possible errors in phonemic-strings which are obtained by some preprocessing of spoken words and then applying statistical decision to resulting features. We set up a new distance measure for measuring the distance between 2 strings. The proposed method uses the new distance measure and the available linguistic information in the form of rules of the following two types; (i) rules obtained from the theory of word formation (from phonemes) in English, and (ii) rules needed to correct some errors made by statistical decision rules used earlier. In an experiment, involving 400 utterances and 40 words, an error correction rate of over 99 percent was achieved using the proposed error correction method.

Error detection in digital systems

Abstract: This invention relates to error detecting arrangements for digital transmission systems. It is particularly applicable to systems in which the line signals are already arranged in or can be converted into a format resulting in what may be termed constant accumulated disparity signals. In a digital transmission system parity information is included so as to cause a toggle in a repeater to take up a particular state immediately following each parity check. This state will only change when an error occurs, or an odd number of errors. When an error has occurred and the toggle has changed its state the new state becomes the normal state and a further change indicates a further error. No special line code is needed and circuitry in the repeater is kept to a minimum. For a binary system it requires an extra digit to be added at reasonable intervals, e.g. after every 100 bits.

Checking error device

Abstract: PURPOSE:To find out an error detection and an error kinds by checking to be a normal error at the time when time lag of constact point operation of duplex systems is over specific time and on the other hand, checking to be an abnormal error at the time when dissidence number of times during fixed time over specific numbers.

Error correction detection system

Abstract: PURPOSE:The information received by transfer equipment is transferred to process stage, and at the same time it is fed into erroe correction circuit. When error is detected, re-test start signal is sent out, and if possible, correction is also carried out simultaneously.

Fault-tolerant modularized arithmetic logic units

Abstract: Use of both parities and residue checks, called a "combination code", can provide a cost-effective error detection and correction and modularized design of arithmetic and logic units (ALU). As codes they compare favorably with the byte-error correcting codes of Neumann and Rao in their information rate, and indeed are better suited for a modularized (or byte-sliced) design of ALU.

Syntactic error correction in programming languages.

Abstract: A technique for syntactic error correction, called pattern mapping, is developed. A pattern is used to describe how to map or change one string into another. Using a preconstructed list of patterns, for each detected error, the first pattern with successful mapping is found and a correction is made based on this pattern.

Error control system

Abstract: PURPOSE:To secure an effective error correction as a whole and thus to insure the sufficiently high quality of the digital information by dividing the digital information into several bit groups and then applying the error control code to each bit group. CONSTITUTION:The analog signal is converted into the natural binary of, for example, 10 bits through A/D converter 11. Then the 5 bits of the higher importance of the digital signal are supplied to error detection code additional circuit 12 with addition of the error control code of, for example, 2 bits featuring a large control capacity. In the same way, the 5 bits of the lower importance of the digital signal are supplied to circuit 13 to be added with the simple error control code of, for example, 1 bit. These signals are transmitted through transmission line 2, and then the error is detected through error detection circuits 32 and 33.

Error correction system of memory

Abstract: PURPOSE:The memory card constitution is determined to m-word x 1-bit formation, at the same time performing parity check in the direction of bit and word respectively. In this way, the memory error correction can be carried out with a simple logic constitution.

Error control circuit

Abstract: PURPOSE:In case plural numbers of parity bits are utilized, to give the function to make parity check to the circuit which produces parity bits, and to promote the simplification of error control circuit.

Correction for memory error

Abstract: PURPOSE:To shorten the executive generation time for the data to be written by generating the error correcting code EEC corresponding to the date to be written parallel with the error detection and correction of the read-out data.