Showing papers on "Error detection and correction published in 1978"

Models for channels with memory and their applications to error control

Abstract: Errors encountered in digital transmission over most real communication channels are not independent but appear in clusters. Such channels are said to exhibit memory, i.e., statistical dependence in the occurrence of errors; and thus cannot be adequately represented by the classical memoryless binary symmetric channel. The existence of memory implies additional capacity. To exploit this through efficient coding schemes, it is necessary to describe and model the underlying statistical structure of the error process. This paper reviews various channel models, noting the interaction between channel modeling and error control.

Combined source-channel coding of images

Abstract: A combined source-channel coding approach is described for the encoding, transmission and remote reconstruction of image data. The source encoder employs two-dimensional (2-D) differential pulse code modulation (DPCM). This is a relatively efficient encoding scheme in the absence of channel errors. In the presence of channel errors, however, the performance degrades rapidly. By providing error control protection to those encoded bits which contribute most significantly to image reconstruction, it is possible to minimize this degradation without sacrificing transmission bandwidth. The result is a relatively robust design which is reasonably insensitive to channel errors and yet provides performance approaching the rate-distortion bound. Analytical results are provided for assumed 2-D autoregressive image models while simulation results are described for real-world images.

On the Theory of Unidirectional Error Correcting/Detecting Codes.

Abstract: : Some basic theory on unidirectional error (i.e. all bits fail in the same direction) correction/detection are presented for binary block codes. Then a new class of codes are constructed which corrects single errors and detects any number of multiple unidirectional errors. Some codes are shown which hither-to-fore known to possess only symmetric error detection/correction properties which can be modified to make them suitable for unidirectional error correction/detection.

On Another Go-Back-N ARQ Technique for High Error Rate Conditions

Abstract: A modification to the basic Go-Back- N ARQ error control technique is described which yields improved throughput efficiency performance for all block error rates.

A forward move algorithm for LR error recovery

Abstract: A "forward move algorithm", and some of its formal properties, is presented for use in a practical syntactic error recovery scheme for LR parsers. The algorithm finds "valid fragment" (comparable to a valid prefix) just to the right of a point of error detection. For expositional purposes the algorithm is presented as parsing arbitrarily far beyond the point of error detection in a "parallel" mode, as long as all parses agree on the read or reduce action to be taken at each parse step. In practice the forward move is achieved serially by adding "recovery states" to the LR machine. Based on the formal properties of the forward move we propose an error recovery algorithm that uses the accumulated right context. The performance of the recovery algorithm is illustrated in a specific case and discussed in general.

Measurement and Generation of Error Correcting Codes for Package Failures

Abstract: Error correcting codes have been successfully employed to correct errors associated with failures in computer memories. A typical code which has found wide application is the binary Hamming code. This code corrects single bit errors. With the advent of large-scale integration (LSI) storage array technology, the likelihood of errors which exceed the correction and detection capability of such a code is significant. A serious and heretofore unanswered question is the error detection capability of a given code which is implemented and decoded for single error correction, particularly when a storage array chip or card carrying multiple bits from the codeword has failed. In order to identify this capability, a new reliability parameter called package detectability is defined. This paper also presents a method for computing package detectability. The analysis has been performed on a number of codes in order to optimize the packaging for maximum detectability. In addition, a class of distance 3 codes with maximal b-bit package detectability is given.

A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems

Abstract: To improve the reliability of computer memories error-correcting and/or error-detecting codes have been successfully used. To provide for error control in systems organized to have b bits per card a new class of codes for simultaneous error correction and error detection is given.

Error repairing method and apparatus for bubble memories

Abstract: An error repairing method and apparatus for a magnetic bubble memory for restoring stored binary data to its original form are described. The method and apparatus are employed to compensate for random error in bubble memories resulting from slipped or disappeared bubbles. The data is coded with an error correcting code, such as a Hamming or Fire code, before storage. The stored, coded data is periodically read from memory and errors are detected and corrected. The corrected, coded data is rewritten into memory. In one embodiment the frequency of the repair cycles is a function of the rate at which errors are detected.

Mobile radio data transmission—Coding for error control

Abstract: Error patterns recorded during mobile radio data transmission experiments in London have been used to assess what error control strategies are required to achieve reliable data communication. The performance of error detecting and correcting codes has been investigated and the effects of varying code parameters explored. Results are given for transmission at 462 MHz using data rates of 1200 b/s and 4800 b/s, and the advantages of using a high data rate are considered. Bit interleaving is shown to be a useful way of dispersing bursts of errors, greatly improving the performance of an error correcting code. Fairly simple coding techniques can give a performance which is adequate for many applications, and a high performance is readily possible.

Dynamic equalization system for dual channel automatic pilot

Abstract: Apparatus for controlling channel equalization in a monitored dual servo channel aircraft automatic flight control system, in which the limits of the equalization control are responsive to the commanded input signal to the control surface. Rate feedback means responsive to the output velocity of each channel are differentially summed and integrated to provide the signals for equalizing the dual servo channels. Limiter means responsive to the commanded input signal varies the limits of the equalization signals to allow very tight error detection thresholds of the system monitor without causing nuisance trips in situations where the system's normal tolerances are large.

Erasure and Error Decoding for Semiconductor Memories

Abstract: In this paper we introduce and evaluate error correction methods which takes into account the special properties of failure modes in semiconductor memories. We assume that the memory faults are of the type stuck-to 1 or 0. Thus the fault, once it has occurred, is located to a specific position in a memory word. The position may be found and this fact makes it convenient to use erasure correction, rather than random error correction.

Evaluations of Error Control Techniques in Both Independent-Error and Dependent-Error Channels

Abstract: Error control techniques in the various digital data transmission systems can be divided into three classes, i.e., classes of forward error correction (FEC), automatic repeat request (ARQ), and FEC embedded within ARQ (Hybrid). We exactly analyze and compare the performances of these error control techniques in both independenterror and dependent-error channels. It is shown that among the various error control techniques the Go-Back-2 ARQ system offers the best performances over a wide range of the channel error rate, i.e., P_{e} \lsim 10^{-4} , regardless of the type of the channel. The various numerical results are shown graphically along with the discussions.

Syntactic Error Correction in Programming Languages

Abstract: A technique for syntactic error correction, called pattern mapping, is developed. A pattern is used to describe how to map or change one string into another. Using a preconstructed list of patterns, for each detected error, the first pattern with successful mapping is found and a correction is made based on this pattern.

Method and system for transmitting and receiving interleaved blocks of encoded data words to minimize error distortion in the recovery of said data words

Abstract: A plurality l of data blocks, each comprised of at least two data words and a parity word associated bit for bit with the data words, together with an error correcting code word associated with each data and parity word, are transmitted in interleaved relation. L data words and associated error correcting code words followed by l parity words and associated error correcting code words and followed by l data words and associated error correcting code words, all transmitted in seriatim, are received and stored, and each error correcting word is decoded to ascertain the presence of an error in each received data or parity word. All of the data words and the parity word in a block are read out simultaneously, together with an indication of the presence of errors in any of the read out data and parity words; and in the event of an error, an erroneous data word is corrected in accordance with the parity word in that block; and if parity correction cannot be achieved, an erroneous data word is replaced by the average of the data word in the preceding and next following data block. In a preferred application, each data word is formed of a plurality of multi-bit samples of, for example, interleaved left channel and right channel audio signals. The overall length of l data words and associated error correcting words plus l parity words and associated error correcting words is greater than the longest expected error length, such as a burst error.

Double bit error correction using double bit complementing

Abstract: An improvement to a semiconductor memory subsystem containing single bit error correction/double bit error detection (SBC/DBD) which provides correction of double bit errors through the utilization of a modest amount of additional circuitry. The present invention accomplishes this result through the technique of sequentially complementing each double bit pair within the semiconductor memory subsystem data word determined to contain a multiple error and rechecking the modified data word with the existing SBC/DBD circuitry, one double bit pair at a time, until it is determined by the SBC/DBD circuitry that such double bit pair complementing has corrected the double bit error.

Arithmetic Codes in Residue Number Systems with Magnitude Index

Abstract: The idea of adding a magnitude index to the residue representation of numbers is reconsidered. The range of a given residue number system is supposed to be divided into intervals of equal width, and the magnitude index of a number X is defined as an integer locating X into one of such intervals. It is shown that the redundancy implied by the use of the magnitude index allows error detection or correction, and the redundancy requirements to detect or correct single residue digit errors are the same as in redundant residue number systems and in product codes in residue number systems. In addition, these codes allow detection of any error affecting the residue representation, provided that the magnitude of the error exceeds a given threshold, and, whenever an error is detected, it is possible to replace the wrong number with an approximation of the correct number.

Computational Aspects of Time Integration Procedures in Structural Dynamics—Part 2: Error Propagation

Abstract: The propagation of computational error in the direct time integration of the equations of structural dynamics is investigated. Asymptotic error propagation equations corresponding to the computational paths presented in Part 1 are derived and verified by means of numerical experiments. It is shown that there exists an implementation form that achieves optimum error control when used in conjunction with one-derivative methods. No such form is found for two-derivative methods. A numerical beating phenomenon is observed for certain implementations of the average acceleration method and the trapezoidal rule, which from an error propagation standpoint, is highly undesirable.

Partial correction of transmission errors in Walsh transform image without recourse to error correction coding

Abstract: A sequency difference detection and correction (sddc) system is described which enables the partial correction of transmission errors in a Walsh-Hadamard transform image to be achieved without channel coding Using a first-order two-dimensional random Gaussian Markov field as the image, the percentage mean-square error in the recovered signal is reduced with the aid of the sddc system by two orders of magnitude for transmission error rates <3%

Writing system for error correction code

Abstract: PURPOSE: To ensure a complete test for the error correction code generator/detector by writing the data given from outside into the memory part in the form of the error correction code. CONSTITUTION: When CPU receives the reading data, the error correction code which is not in agrlement with the reading data is produced to be used as the writing data. Then the address, for example, 100 is issued as the address information, and the address 100 reads out the writing order and the data with register 8 set to "1". This data is sent to driver 9 as the error correction code via error correction code generator/detctor 2 to drive drivers 9 and 10, and the writing data and the error correction code which is not in agreement with the writing data are written into address 100 of memory 1. Then CPU designates address 100 to carry out the reading order, and detector 2 detects the error for the reading data and the error correction code not in agreement with the reading data. Under these conditions, the normal operation is proved. In this way, the various kinds of the tests become possible for detector 2. COPYRIGHT: (C)1980,JPO&Japio

Coding transmission system of picture signal

Abstract: PURPOSE:At a error detection time, the heading data of the next line is searched by using the number of run length codes of the line-- where error detected--, so that the error of a run length code can be prevented surely from affecting the other lines.

A class of multiple-error-correcting arithmetic residue codes

Abstract: AN encoding in residue number systems allows construction of a class of nonlinear arithmetic error-correcting codes. The properties of these codes are further investigated and the redundancy necessary and sufficient to ensure multiple error correction is determined. An error-correcting procedure holding for codes using the minimal redundancy is presented. An error-correcting approach based upon the Euclidean algorithm is also reconsidered and it is shown that its redundancy requirements are lower than previously known.

Error detection system

Abstract: Error detection circuitry for use in a data processing system which utilizes a programmable logic array for controlling, during a write operating mode, the generation of a write error word by an error register, which write error word is thereupon stored together with the associated data words in a data storage device and for controlling, during a read operating mode, the generation of a read error word, the error register thereupon effectively comparing the read error word with the originally stored write error word to produce a remainder word when an error is present.

Error correction system for picture information transmissio n

Abstract: PURPOSE:To send back a reply only when a data retransmission is needed and to switch switch the data to retransmission through a transmitter. In this way, the data transmission time can be shortened.

Pcm signal processor

Abstract: PURPOSE: To prevent the generation of an unpleasant sound based on error detection of error data, by detecting error regenerated data by using a "P" coee and "Q" code, used for error corrections, in addition to a cyclic code. CONSTITUTION: When cyclic code CRC circuit 3 detects an error block while an input signal is sequentially written in memory method 1, an ERROR signal from memory method 1 becomes "1" and DATA is cut off by AND gate circuit 4. Then, correct data are restored by error data correction circuits 9 and 6 using a "P" code and "Q" code and outputted through AND gate circuit 7. Next, when circuit 3 fails to detect the error data, signal ERROR is "0" and error detection signals of the "P" code and "Q" code are outputted as output signal from exclusive-OR gate circuits 13 and 14; and an output from OR gate circuit 10 is "1" and the output signal of circuit 6 is outputted from AND gate circuit 7. If a drop-out generated on a transmission line is extremely long, corrections are impossible and an output from correction disability detection circuit 17 becomes "1", so that interpolation signal generating circuit 12 will output an interpolation signal. COPYRIGHT: (C)1980,JPO&Japio

Device for detecting errors in a digital transmission system

Abstract: A device for detecting errors in digital transmission systems which use a line signal whose digital running total is bounded and can only take n distinct states, e.g. a high data rate digital transmission system. The error detection device comprises a synchronous up/down counter with k bistables which give, in real time, the digital running total, and an end decoder formed by logic gates and which is sensitive to the up/down counter overflowing from either of its upper or lower limit values, the number k being an integer which satisfies the inequality: 2.sup.k >n≧2.sup.k-1.

Adaptive difference detection and correction system for partial correction of transmission errors in linear p.c.m.

Abstract: An adaptive version of the difference detection and correction system for the partial removal of transmission errors in linear p.c.m. speech without the use of channel coding is presented. The improvement in s.n.r. compared to the nonadaptive system is approximately 3 dB for transmission bit error-rates between 0.5 and 5%.

Error-Correcting Codes in Binary-Coded-Decimal Arithmetic

Abstract: Error-correcting coding schemes devised for binary arithmetic are not in general applicable to BCD arithmetic. In this paper, we investigate the new problem of using such coding schemes in BCD systems. We first discuss the general characteristics of arithmetic errors and define the arithmetic weight and distance in BCD systems. We show that the distance is a metric function. Number theory is used to construct a class of single-error-correcting codes for BCD arithmetic. It is shown that the generator of these codes possesses a very simple form and the structure of these codes can be analytically determined.

Error correction circuit having test function

Abstract: PURPOSE:To make it possible to test an error correction circuit by inverting a check bit via a bit inverter circuit and by generating a trouble pattern possibly occurring in the error correction circuit.

Storage system for magnetic data - uses parallel intermediate and serial final transfers and has correction circuits for data retrieval

Abstract: A storage method for coded data divided into individual data blocks involves storage in an magnetic medium of corresp. parallel grouped data signals and error detection and correction circuits for data retrieval. It is designed for high recording density with high error immunity and average expense without necessitating an increase in the degree of redundancy of the code used for recording. Parallel grouped data signals from each block are first intermediately stored and then transferred to the recording medium in series and in accordance with a priority number. For retrieval the data is read from the medium into the intermediate store row by row a corresp. to the parallel group priorities. Reconstructed data groups are then connected and inverted where necessary.