Showing papers on "Error detection and correction published in 1981"

Linear unequal error protection codes

Abstract: The properties of linear codes over GF (q) that provide unequal error protection (UEP) of information digits are discussed. A design is proposed for optimal binary systematic linear UEP codes. Broad classes of iterative and concatenated UEP codes are constructed. Majority decoding algorithms for linear iterative UEP codes are described.

The Correction of I and Q Errors in a Coherent Processor

Abstract: A method is presented for correcting the gain and phase imbalances and the bias errors of the in-phase and quadrature channels of a coherent signal processor [1] by means of coefficients which are derived from measurements of a test signal. The residual errors after correction depend upon the signal-to-noise ratio (S/N) of the test signal and the degree of filtering used in deriving the correction coefficients.

Multiple error detecting and correcting system employing Reed-Solomon codes

Abstract: An error detecting and correcting system implementing the Reed-Solomon (1023, 1006) code having code words whose symbols are elements in the Galois field GF(210) generated by either the primitive polynomial x10 +x3 +1 or x10 +x7 +1. An original data word is encoded to produce a code word w(x) including a first set of checksum symbols appended thereto. Upon retrieval, the data symbols of the receive code word y(x) are encoded by the same encoder that encodes the original data word to produce a second set of checksum symbols. Both sets of checksum symbols are modulo-two summed to produce a residue R(x) from which error syndromes Si can be computed and thus enable rapid correction of errors in the received code word y(x). The system also monitors the number of non-zero symbols in the residue R(x) in order to avoid unnecessary computation of error syndromes Si and other decoding routines, such as when the received code word y(x) is otherwise uncorrectable or when the error exists only in the received checksum symbols, rather than in the data symbols. The distance between code words being (2T+ 2), the error correction routine is bypassed when the number of non-zero symbols in R(x) is less than or equal to T, which indicates that errors only reside in the checksum symbols. When the number of non-zero symbols equals (T+1), the error is uncorrectable. For determining whether a single error exists so that correction can quickly be made, the system also tests whether Si+1 /Si is constant for all error syndromes Si.

The Analysis of Some Selective-Repeat ARQ Schemes with Finite Receiver Buffer

Abstract: In high bit rate data transmission systems with ARQ error control, the throughput efficiency is a function of bit error rate, block or packet size, and the effect of significant round trip delays such as may be experienced in satellite communication systems. The selective-repeat ARQ scheme is capable of providing superior throughput performance independent of round trip delay, but requires excessively large receiver buffers; as a result the inferior GoBack N procedure is commonly adopted. This paper analyzes a class of mixed-mode ARQ protocol models which incorporate a selectiverepeat mode with finite receiver buffer. The protocol models are shown to be amenable to exact throughput analysis, but do assume that the round trip delay is constant and known, blocks are of constant length, and the ACK/NAK signals are returned error free. These assumptions might create difficulties for practical implementation. However, the analytical model results highlight those aspects of ARQ protocols which affect throughput performance as round trip delays increase. The results show that it is desirable for best throughput performance in practical systems that at least the first retransmission of a block following an error should be in the selective-repeat mode to obtain superior performance over GoBack N schemes. Furthermore, alternative secondary retransmission modes are considered which ensure that reliable transmission can be achieved without receiver buffer overflow, even if the selective-repeat mode retransmissions fail. It is shown that the choice of secondary mode does not have a significant effect on the throughput efficiency but has a bearing on complexity.

An Efficient Selective-Repeat ARQ Scheme for Satellite Channels and Its Throughput Analysis

Abstract: In this paper, we investigate a selective-repeat ARQ scheme which operates with a finite receiver buffer and a finite range of sequence numbers. The throughput performance of the proposed scheme is analyzed and simulated based on the assumption that the channel errors are randomly distributed and the return channel is noiseless. Both analytical and simulation results show that it significantly outperforms the go-back- N ARQ scheme, particularly for channels with large roundtrip delay and high data rate. It provides high throughput efficiency over a wide range of bit error rates. The throughput remains in a usable range even for very high error rate conditions. The proposed scheme is capable of handling data and/or acknowledgment loss. Furthermore, when buffer overflow occurs at the receiver, the transmitter is capable of detecting it and backs up to the proper location of the input queue to retransmit the correct data blocks.

Weighted erasure codec for the (24, 12) extended Golay code

Abstract: A codec consists of an encoder and decoder. The encoder provides 12 information bits, 11 parity bits generated according to the polynomial for the (23, 12) Golay code, and an overall parity bit to a transmitter at selected transmit times to form a 24-bit block of data. The decoder is separated into two independent list decoders, a comparator, and common clock generator and output buffers. Each list decoder is divided into a syndrome generator and an overall parity check generator, a syndrome error pattern table, an input buffer, error correction logic, and four-error detection logic. The error pattern table includes a pair of read only memories storing the most likely 12-bit error patterns at each ROM address corresponding to each syndrome. An additional 4-bit output is used to indicate the number of errors in the associated error pattern. The comparator compares the number of errors detected in the two independent decoders and chooses the decoder having the fewer number of errors to provide the corrected data.

Soft decision convolutional code transmission system

Abstract: A data transmission system in which data is transmitted in a form incorporating additional data providing for error correction at the receiver. The data is encoded in a transmitter using a signal mapping system which maps a number of original digits and also digits produced by a convolutional encoder. The data at the receiver is decoded using hard and soft decision decoding which can correct errors in the received data.

A Statistical Analysis of ARQ Protocols Operating in a Nonindependent Error Environment

Abstract: In this paper the behavior of the Stop and Wait and Go Back- N error detection and retransmission (ARQ) protocols in an environment characterized by nonrandom errors are studied. Analytic models are developed for the case that the error process is modeled as a Markovian process. These models may be used to predict performance measures such as expected queue length and expected delay for the case of the Stop and Wait protocol and the Go Back- N protocol when N is very large. The models can also be used to determine maximum throughputs for both protocols. The results of these models are compared with simulation results for the Selective Repeat ARQ protocol.

Burst error performance encountered in digital land mobile radio channel

Abstract: Burst error characteristics are studied by using a Rayleigh and Nakagami-Rice fading simulator. Burst error length distribution estimated with fade duration is described. Thus burst length shortening by means of dual frequency diversity is a promising candidate in order to introduce safely forward error correction (FEC) coding into digital land mobile communication systems.

Pre-emptive retransmission for communication over noisy channels

Abstract: An automatic repeat request (ARQ) scheme which pre-empts the need for the retransmission of data is described. A detailed statistical analysis is carried out and numerical results are presented which show that, under a wide range of high error rate and/or long propagation delay conditions, considerable improvements in performance over the commonly used go-back-N protocol can be achieved with the scheme. The scheme has the advantage of being logically simple and should be capable of straightforward implementation as an extension of software handling the go-back-N protocol.

Refresh and error detection and correction technique for a data processing system

Abstract: A data processing system in which the bits of each stored word in a memory thereof are refreshed periodically. At substantially the same time the refresh operation with respect to each word occurs, an error detection operation also occurs and, if an error is detected in a word that is being refreshed, the error is then corrected and the corrected word is written back into the memory. Thus, errors are continuously being checked with no more use of machine time than is required for the refresh operation. Error correction, when necessary, then takes place at a fixed frequency, a limit thereby being placed on the error correction process. If errors in a word are detected when the word is requested for access by a requestor, the error is corrected before the word is supplied to the requestor but the corrected word is not written back into memory at that time, the word in memory being again detected and corrected at its next refresh operation.

Two bit symbol SEC/DED code

Abstract: A modularized error correction apparatus for correcting package errors is provided by expanding an N bit single error correction, double error detection code to cover N packages of M bits each, so that the Exclusive-OR of all M bit single bit error syndromes in any given package results in a composite syndrome which is unique for each package. See FIG. 2 for the parity matrix H and the matching matrix M for the error correction code.

Digital Communications by Satellite: Modulation, Multiple Access and Coding

Abstract: Digital Communications by Satellite. Error-Rate Performance of Digital Modulation Techniques. Generation and Detection of Modulated Signals. Performance Degradations. Carrier and Clock Recovery. Multi-Phase-Coded Modulation. Frequency-Division Multiple Access. Time-Division Multiple Access. Fundamentals of Error-Control Coding: Forward Error Correction and Automatic Repeat Request. Convolutional Encoding: Viterbi and Sequential Decoding. Error Detection and Correction Using Block Codes. Threshold Decoding of Block and Convolutional Codes. Related Topics and Trends. Appendices. Glossary of Notation. Index.

Error correction device for data transfer system

Abstract: An error correction device for digital data storage and transfer systems wherein data are transferred over a plurality of channels. Synchronously with the transfer of a group of data bits, a coding device forms a first correction bit for a first correction channel and a second correction bit for a second correction channel. The first correction bit is formed on the basis of a second group of data bits, the second correction bits being formed on the basis of a third group of data bits. Each data channel supplies the data of two sub-groups of data bits for this purpose. The delay operator having a length of one bit cell being represented by D, a series of directly successive bits can be represented by a polynomial in D: x0.D0 +x1.D1 +x2.D2 + . . ., in which xj (j =0, 1 . . .) represents the bit value. The quotient of the polynomials relating to the two sub-groups of a data channel is different for each data channel in order to enable correction of an arbitrary error pattern in a single data channel. When the data bits and correction bits are received, a first and a second error elimination bit are calculated from the extracted data bits by using the same algorithm. Comparison of first/second correction/elimination bit produces two error detection bits. When a given number of successive error detection bits do not indicate a discrepancy, the transfer medium is error-free. When a given configuration of discrepancies is detected, a correction vector is formed which indicates, after storage, the channel containing an error, while further error detection bits indicate the error pattern which can thus be corrected.

Forward Error Correction for an ARQ Scheme

Abstract: This paper examines the use of BCH error-correcting codes in improving the performance of a stop-and-wait automatic repeat-request (ARQ) scheme over random error and Rayleigh fading channels. Two models are analyzed. The first model considers the effect of forward error correction on the mean wasted time per message. The second model assumes a Poisson arrival process for the messages and examines the effect of forward error correction on the mean time between the arrival of a message and its successful transmission. In both models, our results indicate that the performance of the ARQ scheme can be substantially improved by the use of forward error correction.

Position error correction equipment

Abstract: Position error correction equipment with which it is possible to perform a backlash correction or a pitch error correction with a high degree of accuracy even if the state of a numerical control machine tool, for instance, temperature, varies. Error correction data groups predetermined by measurement in respective states of the numerical control machine tool are stored in an error storage circuit (MEM) corresponding to the respective states. An error correction data selecting circuit (MPX) selects an error correction data group corresponding to a particular state of the numerical machine tool from the error correction data groups stored in the error storage circuit (MEM). A position correcting circuit (CPG) carries out a position correction by adding a correction pulse to a command pulse or feedback pulse from a position detector through utilization of the error correction data group selected by the error correction data selecting circuit (MPX).

Cryptographic key sharing circuit and method using code correction

Abstract: A circuit and method for sharing a key among n individuals by distributing a secondary key to each of the n individuals such that only k of the n secondary keys are required in order to reconstruct the key, where k may be less than n. The key is encoded into a code vector which is corrupted by combining it with an error vector to yield a corrupted code vector. The secondary keys are chosen so that each one is a mutually exclusive part of the error vector. Reconstructing the key, which is the objective of the process and is analagous to opening a lock, requires correcting the corrupted code vector and transforming the code vector into the key. The corrupted code vector is corrected by a combination of an error correcting code and use of at least k of the secondary keys. Each secondary key can be used to correct the errors introduced in the part of the error vector that it comprises, and if less than k secondary keys are present, then even after the secondary keys have been used to correct the corresponding errors there are too many errors remaining for the error correcting code to correct, resulting in a failure to reconstruct the code vector or key.

Channel Error Recovery for Transform Image Coding

Abstract: A method is presented to automatically inspect the block boundaries of a reconstructed two-dimensional transform coded image, to locate blocks which are most likely to contain errors, to approximate the size and type of error in the block, and to eliminate this estimated error from the picture. This method uses redundancy in the source data to provide channel error correction. No additional channel error protection bits or changes to the transmitter are required. It can be used when channel errors are unexpected prior to reception.

Apparatus and an improved method for processing of digital information

Abstract: An apparatus and method for processing of digital information that includes duplication of information from each channel of a multi-channel recorder on main and backup tracks and provides a combination of error detection apparatus and procedures where data groupings or words on each track are individually subject to four separate tests for detecting errors and provides, from that analysis, for a selection of most likely correct data for further processing. Additionally, further system reliability is obtained by providing circuitry whereby a detected error activates a selection of data groupings coming before and after the detected error, providing where appropriate, for switching from main to backup track data over a certain number of data groupings. There is further provided a unique synchronization coding format with circuitry and a procedure for its use for rapidly acquiring synchronization coding in a data flow and includes an arrangement for averaging the content of first-in-first buffes of each track for controlling tape speed to enable a smooth over-dubbing of information recorded at different times on separate tracks.

Real time fault tolerant error correction mechanism

Abstract: The present invention provides a real-time fault-tolerant hardware error correction device which is typically implemented as a data transfer circuit between a disc memory and a processing unit. It operates in two modes: as an encoding system and error detector on a disc write, and as a decoding system and error corrector on a disc read. In its first mode, each block of data from the processing unit is encoded with an error syndrome as it is transmitted to the disc memory. Two identical linear feedback shift registers (LFSR's) are used for error detection purposes. In its second mode, the same two LFSR's are implemented with a buffer memory to achieve real-time error correction. Data flow to the LFSR's from the disc memory is alternated block-by-block, one block being received by one LFSR and the succeeding block being received by the other LFSR. At the same time that data is channeled to a particular LFSR, it is channeled synchronously to the buffer memory. While one LFSR is decoding the incoming block, the other LFSR is providing output signals to correct the previous data block which is leaving the buffer memory as new incoming data arrives.

Method for error correction

Abstract: A method of error correcting pulse code modulated data is provided in which the data words and check words are encoded in an error correcting block. The encoded data words may have one of at least two error conditions associated therewith, and the presence of each type of error condition is detected for each word. A corresponding pointer identifying one of these error conditions is added to the data words. In subsequent processing, the kinds of pointers added are discriminated, and the data words are processed on the basis of the results of this discrimination to correct or compensate for error conditions in the data words.

Method and apparatus for encoding digital with two error correcting codes

Abstract: Successive data words are distributed to a plurality of respective channels to form successive data blocks, each data block being comprised of the data words in the plural channels. A first error correcting code is generated as a function of the words included in the data block, this first error correcting code being adapted for use in correcting at least one word which may be erroneous in the data block, as when the data block subsequently is received or reproduced. The data words included in the data block are selectively delayed, by different respective time delays, to form a time-interleaved data block comprised of time-interleaved data words. A second error correcting code is generated as a function of the words included in the time-interleaved data block, this second error correcting code being adapted for use in correcting at least one word which may be erroneous in the time-interleaved data block, as when the time-interleaved data block subsequently is received or reproduced. The first and second error correcting codes and the time-interleaved data block are combined to form a transmission block which may be transmitted or recorded on a suitable record medium.

An Error Detection Model for Application During Software Development

Abstract: A variation of the Jelinski/Moranda model is described. The main feature of this new model is that the variable (growing) size of a developing program is accommodated, so that the quality of a program can be estimated by analyzing an initial segment of the written code. Two parameters are estimated from the data. The data are: a) time separations between error detections, b) the number of errors per written instruction, c)the failure rate (or finding rate) of a single error, and d) a time record of the number of instructions under test. This model permits predictions of MTTF and error content of any software package which is homogenous with respect to its complexity (error making/finding). It assists in determining the quality, as measured by error contents, early on, and could eliminate the present practice of applying models to the wrong regimes (decreasing failure rate models applied to growing-in-size software packages). The growth model is very tractable analytically. The important requirement for applications is that the error-making rate must be constant across the entire software program.

Method and apparatus for transmitting a digital signal

Abstract: A PCM digital signal is provided with double-interleaving and error-correction encoding to protect against errors occurring during transmission, which can be carried out by magnetic recording and reproducing. The PCM signal is processed as error correcting blocks of several data word sequences and an associated error correction word sequence, and the double-interleaved sequences are then transmitted as transmission blocks. Up to one erroneous word in each error correction block can be corrected by using the error correction word sequence. Any uncorrectable word can be compensated by substituting a synthetic word interpolated from immediately preceding and following data words known to be correct. The distance between successive data words is made as great as possible so that a long burst error is unlikely to affect the ability to compensate uncorrectable errors. To achieve this, alternate words of the PCM signal are distributed to odd and even groups of sequences, and the interleaving is carried out by imparting different delay times to the respective sequences such that the greatest delay time imparted to the odd sequences is less than the shortest delay time imparted to the even sequences. The error correction word sequence is provided with a delay time intermediate the greatest delay time of the odd sequences and the shortest delay time of the even sequences.

Parallel/series error correction circuit

Abstract: In a data processing system, an error correcting circuit (302) is connected in a bridging mode (parallel) to the data bus (RDB) which interconnects a processor (301) and a memory (303). While in this mode the error correction circuit (302) does not delay the transmission of the memory words, but simply monitors the data. If an error in the data is detected, an error signal is generated on the next processor microcycle, the processor (301) aborts its present operation and then fetches the corrected data from the error correction circuit (302). If the frequency of errors increase or if a permanent error is detected, the error correction circuit (302) switches to an in-line mode (series) thus causing a delay in the transmission of each memory word until the error check is complete.

Data recording system

Abstract: PURPOSE:To increase the reliability for a data recording system of a disk, by adding an error correcting code to the address part of a block and adding an error detection correcting code which is common with both the data and address parts to the data part of the block to perform the recording. CONSTITUTION:A mark 1 showing the block starting position and then an address part 2 and a data part 4 are added to a block format which performs the reading/writing on a magnetic disk. A gap 6 is secured among these mark 1 and the parts 2 and 4 respectively. An error detecting code 3 is added at the position immediately after the part 2, and at the same time an error detection correcting code 5 common with parts 2 and 4 is added at the position right after the part 4. In such way, the contents read into a buffer 12 is fed to an error detecting code circuit 13 and an error detection correcting code circuit 14 to be processed there in the reading/writing mode. As a result, a data process is possible with high reliability with a short block length.

A PCM signal processor

Abstract: A pulse code modulation signal processor extracts signal processor control words from a serial pulse code modulation data stream also containing error detection and correction codes. The PCM signal processor includes a serial-to-parallel converter to convert the serial PCM data stream into the signal processor control words in a parallel format, an error detector connected to the serial-to-parallel converter for forming an error signal indicating the presence or absence of an error in the control words, registers for storing first signal processor control words when the error signal indicates the absence of an error in the signal processor control words and for preventing the storage of the signal processor control words when the error signal indicates the presence of an error in the signal processor control words, and a transient error correction circuit for storing second signal processor control words when the error signal first indicates the presence of an error and subsequently indicates the absence of an error and when the second control signals of two successive PCM data streams are equivalent.

Correction system for readdin error

Abstract: PURPOSE:To decrease the processing time of CPU required for correction, by transferring the error pattern data for the read-in error of the data area and ''00'' data in other areas to the channel for error correction CONSTITUTION:If there is read-in error possible for correction in the data area of the memory disc 5, the byte in error and the number of bytes are obtained from the data area 10 of the memory disc 5 with the control unir 4 and they are respectively stored in the error pattern register 25, and error displacement register 26 For the read-in error of the data area, the error pattern data is transferred to the channel 2 and in other areas, ''00'' data is to the channel 2 In case of the former, the data in the CPU memory and the error pattern data are operated for exclusive logical sum and the result is restored in the CPU memory In case of the latter, the byte counter 21 and the memory address register 12 are simply renewed

Fault and error detection arrangement

Abstract: A fault and error detection arrangement for detecting transmission and routing errors made by systems in which a central data transmitter/receiver (601, 610) bidirectionally intercommunicates with peripheral circuits (620) through an interconnection arrangement (604). The parity bits of certain data words transmitted by the central data transmitter (601) are intentionally inverted by a central parity inverter (602), in a known sequence. Data words transmitted by the central data transmitter (601) are routed by the interconnection arrangement (604) to the peripheral circuits (620) where parity is checked by a peripheral parity checker (621) and a parity invert signal is generated when an inverted parity data word is found. A peripheral parity inverter (623) included in each peripheral circuit (620) responds to the parity invert signals by inverting the parity bit of the next data word transmitted by a peripheral data transmitter (622) also included in each peripheral circuit (620). The data words transmitted by each peripheral circuit (620) are routed by the interconnection arrangement (604) to a central parity checker (610) in time-multiplexed channels. By the operation of the above arrangement, a known sequence of data words having inverted parity bits should be received by the central parity checker (610). An error signal generator (612) generates error signals when deviations from the expected sequence are detected.