Showing papers on "Error detection and correction published in 1982"

A Hybrid ARQ Scheme with Parity Retransmission for Error Control of Satellite Channels

Abstract: This paper presents a new type of hybrid ARQ scheme for error control in data communication systems. The new scheme is based on the concept that the parity-check digits for error correction are sent to the receiver only when they are needed. Normally, data blocks with some parity-check bits for error detection are transmitted. When a data block D is detected in errors, the retransmissions are not simply repetitions of D , but alternate repetitions of a parity block P(D) and D . The parity block P(D) is formed based on D and a half-rate invertible code which is capable of correcting t or fewer errors and simultaneously detecting d (d > t) or fewer errors. When a parity block is received, it is used to recover the originally transmitted data block either by inversion or by decoding operation. The repetitions of the parity block P(D) and the data block D are alternately stored in the receiver buffer for error correction until D is recovered. We show that the proposed hybrid ARQ scheme provides both high system throughput and high system reliability. It is particularly attractive for error control in high-speed data communication systems with significant roundtrip delays, such as satellite channels.

Concurrent Error Detection in ALU's by Recomputing with Shifted Operands

Abstract: A new method of concurrent error detection in the Arithmetic and Logic Units (ALU's) is proposed. This method, called "Recomputing with Shifted Operands" (RESO), can detect errors in both the arithmetic and logic operations. RESO uses the principle of time redundancy in detecting the errors and achieves its error detection capability through the use of the already existing replicated hardware in the form of identical bit slices. It is shown that for most practical ALU implementations, including the carry-lookahead adders, the RESO technique will detect all errors caused by faults in a bit-slice or a specific subcircuit of the bit slice. The fault model used is more general than the commonly assumed stuck-at fault model. Our fault model assumes that the faults are confined to a small area of the circuit and that the precise nature of the faults is not known. This model is very appropriate for the VLSI circuits.

Implicit Adaptive Control for a Class of MIMO Systems

Abstract: Two implicit model reference adaptive control algorithms for multi-input multi-output systems are developed These algorithms do not require either satisfaction of the perfect model following conditions or explicit parameter identification The first algorithm ensures asymptotic stability of the output error provided that the output stabilized plant transfer matrix is strictly positive real The second algorithm guarantees a bounded error under less restrictive conditions The algorithms are applied to the lateral axis of an F-8 aircraft

An Improved Selective-Repeat ARQ Strategy

Abstract: A new procedure for handling retransmissions in a selective-repeat ARQ system is proposed. This procedure can operate with a receive buffer of minimal size; in addition it places little computational load on the transmit and receive processors. The procedure is simple enough that its throughput can be calculated exactly. Analysis of this strategy shows that: 1)it yields higher throughput than earlier ARQ techniques; 2) for modest receive buffer size, its throughput differs little from channel capacity; 3) as buffer size increases, throughput approaches channel capacity. The final section of the paper considers the performance of ARQ systems on channels in which errors occur in bursts. It indicates that on reasonably good channels, error burstiness has little effect on throughput.

On the Probability of Undetected Error for Linear Block Codes

Abstract: The problem of computing the probability of undetected error is considered for linear block codes used for error detection. The recent literature is first reviewed and several results are extended. It is pointed out that an exact calculation can be based on either the weight distribution of a code or its dual. Using the dual code formulation, the probability of undetected error for the ensemble of all nonbinary linear block codes is derived as well as a theorem that shows why the probability of undetected error may not be a monotonic function of channel error rate for some poor codes. Several bounds on the undetected error probability are then presented. We conclude with detailed examples of binary and nonbinary codes for which exact results can be obtained. An efficient technique for measuring an unknown weight distribution is suggested and exact results are compared with experimental results.

Errors in fixed and moving frame of references - Applications for conventional and Doppler radar analysis

Abstract: Techniques for the correction of errors in Doppler radar scans due to advection effects are presented. A moving frame of reference is shown to be useful in least-squares estimates with stationary observations expressed in scalars or Cartesian coordinates. For non-Cartesian coordinates, such as the deduction of radial velocities from triple Doppler radar data, an integral is defined for accounting for advection effects and consequent coordinate transformations. The multiple radars are necessary for unambiguous characterization of the horizontal wind velocity. A scale analysis is employed to estimate errors with and without the error correction procedure. Improvements in correlations between scans are demonstrated when the error correction method is used.

Adaptive misposition correcting method and apparatus for magnetic disk servo system

Abstract: A misposition correction system for correcting misposition errors due to spindle runout and other slowly varying errors in a servo positioning system of a magnetic disk storage device The system includes means for dynamically measuring misposition error with respect to a data track centerline using an anti-aliasing analog filter, means for digitizing the measured analog signal and for removing selected harmonics of the fundamental-frequency of the resulting cyclic error signal, means for transforming the digitized error signal by a matched digital filter whose transfer function contains independently adjustable DC gain, fundamental-frequency gain, and phase lead components thereby to generate a misposition error correction signal that matches the electrical and mechanical response characteristics of the servo system Further, the system includes means to iteratively refine the correction signal by re-applying it to the servo controller when measuring misposition errors with respect to the data track centerline The system stores separate misposition correction signals for each transducer on the disk so that one of several correction signals can be selected depending on which transducer in the device is selected The system further includes means for generating a bias force correction signal to correct for non-linear position errors resulting from variations in bias forces acting on the transducer carriage over its range of radial displacement

Systematic memory error detection and correction apparatus and method

Abstract: A systematic data memory error detection and correction apparatus periodically reads data from each addressable memory location, determines the presence or absence of an error in the addressed data memory location and, if an error is detected, corrects the error and writes the corrected data back into the addressed memory location. The apparatus may include circuitry for logging those areas of the data memory where errors have been detected, such logging showing either the address location where an error is detected or alternatively indicating the repetitiveness of an error at any particular addressed memory location. Such data logging facilitates determination of hardware or "hard" type errors as distinguished from non-hardware or "soft" type errors. The latter type errors are typically found in dynamic random access memories (dynamic RAM's) which occasionally and randomly have errors due to bombardment of cosmic energy and alpha particles, the latter typically due to minute radioactive elements in silicon materials used in the fabrication of such memories. When the present apparatus is used in conjunction with dynamic RAM's, the error detection and correction is typically performed during "refresh" times which are necessary for maintaining proper stored charge in such devices. By so doing, the access performance of the memory is not degraded by the error detection and correction apparatus.

Onboard clock correction by means of drift prediction

Abstract: In an on-board satellite clock correction system of the type wherein phase errors between the satellite clock and a ground-based clock are determined and a clock correction value sent to the satellite, the clock correction value is determined by curve-fitting the determined phase errors in accordance with a polynomial function, updating the polynomial function coefficients so as to minimize discrepancy between the determined phase errors and those according to the polynomial function, predicting a clock drift in accordance with the polynomial function and calculating an error correction value in accordance with the predicted clock drift.

An Adaptive Array Signal Processing Algorithm for Communications

Abstract: An algorithm is described for initial synchronization in a communication system with a digital adaptive array. This algorithm can also be used for message extraction. A set of consecutive complex video samples of the array output is processed to obtain optimum adaptive array weights, based on a least mean square (LMS) error criterion. This computation is performed for each of the possible alternative signals which may be present during an observation interval. The correct synchronization time or message symbol is selected as the one which yields the minimum LMS error. Assuming orthogonality of the alternative codes, a probability distribution for the output of this processor has been derived.

Systematic error correction in bar code scanner

Abstract: A technique for compensating for systematic errors in printing or reading bar codes is disclosed. Label decoding always begins with a center character (32) and proceeds one character at a time toward a margin. When bar-space pair measurements indicate an ambiguous character (which can only be fully decoded using bar width measurements) error correction is based on the characteristics of the adjacent, previously decoded character.

An Analysis of a TDMA Channel Using Stop-and-Wait, Block, and Select-and-Repeat ARQ Error Control

Abstract: In this paper, the multiaccess broadcast communication channel operating under a TDMA control discipline and employing an ARQ scheme is examined. The generating function of the message delay distribution is derived. The effects of nonzero bit error rates on multipacket messages under several stop-and-wait and block ARQ systems are incorporated. Numerical results for the steady-state mean and variance of the message delay are presented for a stationary transmission error process model in which errors occur as independent events. Results for this channel under a select-and-repeat ARQ system are developed for single packet messages. Stability requirements are stated, useful bounds on the average message delay at steady state are derived, and numerical examples are presented.

The Reliability of Memory with Single-Error Correction

Abstract: This correspondence contains the derivation of the reliability, as a function of time, of semiconductor memory with single-error correction. The results are applicable to a wide range of memory organizations.

FM/CW radar linearization network and method therefor

Abstract: An FM/CW radar linearization network provides target identification data discriminating a target from background reflections and/or false targets by compensating for random variations in the linearity of the frequency sweep of the radar transmitter in the processing of the radar receiver signal, the latter being characteristic of the range and physical size of the target. Linearization is achieved by sampling the transmitter signal, generating an error signal proportional to and indicative of any deviations in the frequency sweep of the transmitter from that for linear operation, and applying that error signal to correct the target data signal, thereby frequency normalizing the same for processing and utilization. A number of alternatives in respect of the development of an appropriate error signal and further alternatives in its use as the basis for data correction are disclosed, including sampling of the transmitter in respect of the phase angle over a predetermined period or the time for a predetermined number of cycles, in order to develop an error signal proportional to and indicative of any deviations in the frequency sweep of the transmitter from that were its operation linear; while data correction may be made in one of a number of alternative ways, including phase rotation of the raw target data input signal, time-shifting of the sampling rate of such data, or frequency mixing the raw target data with an error control signal. Representative networks and suitable methodologies to achieve linearization are disclosed herein.

Error-correction format for digital television signals

Abstract: An error-correction format for transmitting digital television signals comprises segments of data, which segments may for example represent 48 successive horizontal lines of a television field. The segment comprises, for example, data groups n to n+23 and a final group n+24 which forms a vertical parity check group. Each of the data groups n to n+23 comprises m blocks, and each block comprises a synchronization and address sub-block followed by s data sub-blocks, each data sub-block being followed by respective inner code protection bits for providing error protection for the immediately preceding data sub-block, and finally followed by a cyclic redundancy check code for providing error protection for the s data sub-blocks in the block. The vertical parity group n+24 is just the same in format as the other groups n to n+23, but each sub-block thereof is made up of vertical parity check words which form an outer error correcting code in place of data words.

Data receivers incorporating error code detection and decoding

Abstract: A data receiver is required to detect successive 50-bit frames of data which are transmitted without any pause between frames and with a start bit value of 1 as the only start-of-frame indication. Error detection and correction is obtained by appending at the transmitter a 13-bit check word to 36 data bits (and the start bit), the value of the check word being chosen such that division of the error-free composite 49-bit code word by a predefined generator polynomial yields a syndrome (remainder) of zero. Calculation of a new syndrome value by the receiver at the speed necessary during initial frame synchronization (i.e. for each successive bit) is effected with an iterative procedure in which the previous syndrome value is left-shifted one place and the newly received digit is appended to it; the generator polynomial is added to the result by modulo-2 arithmetic if the most significant digit of the shifted syndrome word is a 1; and the remainder of -2 49 divided modulo-2 by the generator polynomial is added to the result of the previous step by modulo-2 arithmetic if the digit received 49 bits before the newly received digit is a 1.

Error correcting code decoder

Abstract: A method and apparatus which can significantly reduce the matched filter requirements in decoding cyclic block codes, and is particularly advantageous for decoding maximal length block codes, and other cyclic block codes in which the number of codewords is ≦2k where k is the number of data bits encoded into each codeword. The signal containing the codeword is concatenated with itself, then the concatenated signal is applied to a matched filter to provide a peaking signal at some point in time as the concatenated signal is passed through the matched filter. The position of the peaking signal relative to a predetermined instant of time is sensed whereby the identity of the codeword (and thus data) can be determined.

Principles of Data Structure Error Correction

Abstract: Error correction in robust data structures is a difficult problem. Several algorithms for correcting structural errors, in certain list and tree structures, are now known. These algorithms have been examined to determine common design features which may prove useful in the design of correction algorithms for other structures. This paper presents a summary of the algorithms studied and the design principles which were derived. The paper is not a "cookbook" for constructing error correction algorithms, but should prove useful to those designing such algorithms. Implications for the design of robust data structures, so that correction may be done easily, are also briefly discussed.

Error-correction technique for random-access memories

Abstract: On-chip error correction for random-access memories is not very popular because of the high overhead necessary. This paper presents a technique that performs a single-bit correction and a double-bit detection on clocked memories where all column data is internally available, with an area penalty of less than 20 percent. The timing overhead for on-chip implementation is less than the time required to generate a parity bit. The detection and correction operation is transparent to the user and does not require different cycle times for the detection and the correction.

Data transmitting method

Abstract: PURPOSE: To increase correctable burst error length, by arranging one parity P at the center part of a block having the large possibility of an error incorrectable state for complete cross interleaving, and arranging the other parity Q at a terminal of the block. CONSTITUTION: Reproduced data read out of an RAM3 or 4 is supplied to a P and Q encoder and decoder 6 to make an error correction using parity and the error-corrected data is written in the RAM3 or 4 again. This error correction requires only information on the occurrence of an error, and therefore an error word itself is not written in the RAM3 or 4. The reproduced data after the error correction read out of the RAM3 or 4 is supplied to a correcting circuit 23 to perform the mean value interpolation of an error-incorrectable word. The output of this correcting circuit 23 is converted by a D/A converter 24 into an analog signal to obtain an audio signal at an output terminal 25. COPYRIGHT: (C)1983,JPO&Japio

Error correcting code processing system

Abstract: A high speed code processing system for error correcting code is disclosed. It uses bit parallel residue generation for cyclic codes. This minimizes the time delay for cyclic code processing. Residue generation of the bit string is accomplished by processing multiple bits in each clock time instead of the conventional bit-by-bit implementation. Thus, the checkword calculation and the syndrome calculation are accomplished at a significantly higher speed than the conventional shift register approach to provide a system capable of on-line residue generation.

A Comparison of Block and Convolutional Codes in ARQ Error Control Schemes

Abstract: ARQ methods of error control can considerably improve the reliablity of data transmission in such areas as satellite communications, computer networks, etc. A number of ARQ schemes using both block and convolutional codes have appeared in the literature. In this paper, the following problem is addressed. Given two different implementations of an ARQ scheme, one using a block code and the other using a convolutional code, such that the bit error probability of both implementations does not exceed some specific value, which implementation has the higher throughput and under what conditions will it be attained? The comparison is made for three basic retransmission schemes using both hybrid and pure ARQ: stop-and-wait, go-back- N , and selective repeat. Numerical estimates of the throughput were obtained using approximate theoretical expressions for BCH codes and simulation results for sequential decoding of rate 1/2 convolutional codes. Parameters optimizing the performance of both block and convolutional codes for different channel conditions and round trip delays were found and were used to obtain these numerical estimates. Comparison of the quantitative results indicates a trend toward preferring convolutional codes as delay and/or block length increases. A binary symmetric channel with noiseless feedback was assumed. Possible implications for the Gaussian channel are also discussed.

Orchard error correction system

Abstract: An error correcting system involves the addition of parity type correction bits to each word in a series of digital word forming data to be transmitted or processed. When a person is passing an orchard where a field of partially grown trees are planted, you can look directly down the rows of trees perpendicular to the side of the field, and you can also look at an angle 45 degrees forward and down an open path 45 degrees to the rear of your path along the side of the orchard. In the present system, the error correction parity bits are summed over digits representing more then one vector through the words of data information, which are quite similar to the prospect along three different vectors in an orchard, as mentioned above. Following transmission through a data link in which errors may be introduced by the reversal of certain bits, the bits are summed along the same vectors in an error correcting circuit, and a pattern of error correction "flag" bits is associated with each word with the error correction bits representing sums along vectors which did not have the predetermined parity. A first error correction circuit is provided for correcting single errors within the pattern covered by the vectors; and a second multiple error correcting circuit receives the data from the first error correction circuit after the single errors have been corrected both in the data, the associated correction bits, and in the associated error detection bits, and the residual multiple errors are then corrected in this second error detection circuit. Additional levels of error correction can also be provided by increasing the number of vectors encoded and the number of correction circuits.

Deterministic permutation algorithm

Abstract: Swapping of bits between different words of a memory is accomplished by reference to data on bad bits in the memory. This data controls address inputs to each bit in a memory word so that any word with multiple uncorrectable data is changed to a correctable data word by placing one or more of the bad bits in the word into another word of the memory. The swapping is done by an exclusionary process which deselects certain combinations of addresses thereby limiting the selection process to other combinations. The process can involve categorizing of failures in accordance with type and performing algorithm operations which identify combinations of bit addresses that would result in combining the failures so that there are more errors in any memory word than would be correctable by the error correction code monitoring the memory.

Error detection and recovery in a dynamic planning environment

Abstract: In this paper a set of techniques for error detection and recovery is proposed. These techniques augment a planning system (the ELMER system) which already has many features for preventing execution errors but has few features for handling errors that can't be prevented. The error handling techniques presented in this paper depend for their effectiveness on the close co-operation of the planning, execution and knowledge base components of the system, and especially make Use of knowledge learned from the earlier execution of other plans.

Digital signal transmission system using catv line

Abstract: PURPOSE:To realize transmission of a large quantity of digital signals with free division of the corresponding block length, by reducing the redundancy of an error correction code of a CATV system. CONSTITUTION:The digital signals are transmitted to plural channels, and at the same time an error correction code is added to each channel to increase the block length of an information signal and to reduce the redundancy occupied by the error correction code. Thus the block length of the information signal can be used with free division. The figure A shows a stereo channel containing 34 bits in all of an L channel (16 bits), an R channel (16 bits) and the service bit (2 bits). The figure B shows a word containing 162 bits of channels A, B, C and D (34 bits each), a BCH code (16 bits) and a synchronizing (SYNC) code (10 bits). The figure C shows a frame containing 32 words (5184 bits). Thus the signal formats are shown in these figures. The transmission capacity (transmission speed) using 2 series (quadruple level) of such signal formats is within an allowable range. This is possible enough to transmits the digital signals via a transmission line having a band width of a channel of a TV.

Memory system with error detection and correction

Abstract: A memory system comprised of M memory modules where M-1 of the modules are for storing data bits and the Mth modules is for storing system parity bits corresponding to the data bits stored in the other M-1 modules. Each module has R·C bit locations organized into W internal words of L bits and includes a parity array for storing one parity bit for each internal word, where L is greater than 1, and RC=WL. Each module includes means for reading an internal word and for reading-out a particular subset of the L bits of that internal word. Each module includes means for checking the parity of a selected internal word and for producing a first parity signal indicating whether or not it is correct. The memory system includes means for checking the parity of the selected subsets read out from the M modules and for producing a system parity signal indicating whether the parity of the M subsets is correct. When the first parity signal and the system parity signals indicate the presence of parity errors the subset read out from a module whose first parity signal indicates the presence of a parity error is corrected.

Method for adding error correcting code to variable length data

Abstract: PURPOSE:To prevent occurrences of mistakes in error correction, by adding an error correcting code after fixed length is secured by adding dummy code to data corresponding to the final end of divided variable length data. CONSTITUTION:Picture information in a page buffer 2 is condensedly processed at every line, and, when the picture information at the end of a line is read out, an end-of-line signal EOL is detected by an EOL detecting circuit 25 and a signal ''1'' is outputted from the circuit 25. Therefore, a read signal from the buffer 2 is obstructed by an inverter circuit 27 and an AND circuit 23, and, at the same time, a dummy code generating circuit 31 is started to operate by the output of another AND circuit 30 and a dummy code signal F is supplied to an optical disk device 10 through OR circuits 26 and 21. In this way, the length of picture information at the end of line can be adjusted to a fixed length by adding the dummy code.