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Showing papers on "Error detection and correction published in 1984"


Journal ArticleDOI
TL;DR: In this article, a survey of various types of ARQ and hybrid ARQ schemes, and error detection using linear block codes is presented, where a properly chosen code is used for error detection, virtually error-free data transmission can be attained.
Abstract: ERROR DETECTION incorporated with automatic-repeatrequest (ARQ) is widely used for error control in data communications systems. This method of error control is simple and provides high system reliability. If a properly chosen code is used for error detection, virtually error-free data transmission can be attained. This paper surveys various types of ARQ and hybrid ARQ schemes, and error detection using linear block codes.

976 citations


Journal ArticleDOI
TL;DR: The cost of a number of sequential coding search algorithms is analyzed in a systematic manner and it is found that algorithms that utilize sorting are much more expensive to use than those that do not; metric-first searching regimes are less efficient than breadth-first or depth-first regimes.
Abstract: The cost of a number of sequential coding search algorithms is analyzed in a systematic manner. These algorithms search code trees, and find use in data compression, error correction, and maximum likelihood sequence estimation. The cost function is made up of the size of and number of accesses to storage. It is found that algorithms that utilize sorting are much more expensive to use than those that do not; metric-first searching regimes are less efficient than breadth-first or depth-first regimes. Cost functions are evaluated using experimental data obtained from data compression and error correction studies.

623 citations


Journal ArticleDOI
C. L. Chen1, M. Y. Hsiao1
TL;DR: The construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and for each class of codes the number of check bits required for commonly used data lengths is provided.
Abstract: This paper presents a state-of-the-art review of error-correcting codes for computer semiconductor memory applications. The construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and for each class of codes the number of check bits required for commonly used data lengths is provided. The implementation aspects of error correction and error detection are also discussed, and certain algorithms useful in extending the error-correcting capability for the correction of soft errors such as α-particle-induced errors are examined in some detail.

589 citations


Journal ArticleDOI
TL;DR: A large class of block and convolutional real-number single-error-correcting codes, derived from similar codes over GF(p) , are presented and it is shown that maximum distance separable real- number BCH codes exist for all nontrivial values of N and K.
Abstract: Error-correcting codes defined over the real-number and complex-number fields are introduced. The possibility of utilizing realnumber arithmetic permits the codes to be implemented with operations normally available in standard programmable digital signal processors by methods which are discussed. Hadamard and discrete Fourier transform codes are presented for block coding, and the latter are seen to be cyclic and to include the class of BCH codes. It is shown that maximum distance separable real-number BCH ( N, K ) codes exist for all nontrivial values of N and K . A large class of block and convolutional real-number single-error-correcting codes, derived from similar codes over GF(p) , are presented. Both block and convolutional codes are seen to be describable by the z -transform in a manner which emphasizes their similarities to conventional digital signal processing structures such as digital filters and digital filter banks. Methods for correcting weight t and t + 1 errors in a t error-correcting code are demonstrated and interpreted; in particular, the use of a VLSI digital signal processor for implementation of an algorithm for correcting almost all double adjacent error patterns in a single-error-correcting convolutional code is discussed.

196 citations


Journal ArticleDOI
TL;DR: This paper reconsiders vector quantization jointly optimizing source coding and channel coding, and proposes a new vector quantizer for noisy channels that is improved without adding the redundancy for error correction and becomes significant for highly correlated sources and longer block length.
Abstract: Recently, vector quantization has become noted as a highly efficient coding method of image and voice data. So far, many of the highly efficient coding problems, or service coding problems, have been studied separately from channel coding problems. This paper reconsiders vector quantization jointly optimizing source coding and channel coding, and proposes a new vector quantizer for noisy channels. Vector quantizers for binary symmetric channels are designed for memoryless Gaussian source, Gauss-Markov source and the real images, and are compared with the conventional vector quantizer which does not take account of channel errors. As a result, it is shown that the performance of the proposed vector quantizer is improved without adding the redundancy for error correction, and the improvement of the performance of the proposed vector quantizer for noisy channels over the conventional vector quantizer becomes significant for highly correlated sources and longer block length.

164 citations


Journal ArticleDOI
TL;DR: It is found that to achieve the maximum throughput, n should be small, which implies that coding schemes with short PN sequences and low rate codes are superior in terms of throughput or antijam capability.
Abstract: We consider the use of error correction codes of rate r on top of pseudonoise (PN) sequence coding for code division multiple accessing of the spread spectrum channel. The channel is found to have a maximum throughput of 0.72 and 0.36 based on the evaluation of channel capacity and cutoff rate, respectively. More generally, these two values are derived for given bandwidth expanding n/r versus n/N where n is the length of the PN sequence and N is the number of simultaneous users. It is found that to achieve the maximum throughput, n should be small. This implies that coding schemes with short PN sequences and low rate codes are superior in terms of throughput or antijam capability. The extreme case of n = 1 corresponds to using a very low rate code with no PN sequence coding. Convolutional codes are recommended and analyzed for their error rate and decoding complexity.

163 citations


Journal ArticleDOI
TL;DR: The results show that the MDS codes are effective for both pure error detection and simultaneous error correction and detection.
Abstract: In this paper we investigate the performance of maximum-distance-separable codes with symbols from GF(q) when they are used for pure error detection or for simultaneous error correction and detection over a q -input and q -output discret memoryless channel with symbol error probability e. First we show that the probability of undetected error for an MDS code used for pure error detection is upper bounded by q^{-r} and decreases monotonically as edecreases from (q - 1)/q to 0, where r is the number of parity-check symbols of the code. Then we show that the probability of undetected error for an MDS code used for correcting t or fewer symbol errors is upper bounded by q^{-r} \Sum\min{i=0}\max{t}(\min{i} \max{n})(q - 1)^{i} and decreases monotonically as e decreases from (q - 1)/q to 0. These results show that the MDS codes are effective for both pure error detection and simultaneous error correction and detection.

106 citations


Journal ArticleDOI
E.L. Cusack1
TL;DR: A class of block codes is described which exploits the properties of quadrature amplitude modulation signal constellations whose points lie on a square grid and offer coding gains of 3 dB and 4.5 dB.
Abstract: A class of block codes is described which exploits the properties of quadrature amplitude modulation signal constellations whose points lie on a square grid. The simplest codes in the class have block lengths 4 and 8 and offer coding gains of 3 dB and 4.5 dB, respectively.

105 citations


Patent
15 May 1984
TL;DR: In this paper, the Reed/Solomon algorithm is used to detect and correct errors in a 32-block data field, where rows and columns are replaced by auxiliary check words derived from the remainder of the data field of the block.
Abstract: Data for recordation on a video disc is given multi- redundancy at block, field and group levels. Data and error-correction redundancy is preferably written in a format of 32 rows by 32 columns (32x32) of 8-bit words. Raw data is filled typically serially row by indexed row to a 30x30 interval with at least one and preferably 3 words being auxiliary check words derived from the remainder of the data field of the block. Block filling is completed with the addition of preferred Reed/Solomon error-correction redundancy filling two rows for column error detection and correction and two columns for row error detection and correction. The data fill rows and columns zero through 29 and the error-correction redundancy filling rows and columns 30 through 31. Thirty blocks, so prepared, are processed to obtain two redundant blocks, completing a 32-block data field. Writing the data onto the video disc occurs with a three-dimensional diagonal interleave at the field level. After interleave each field is additionally XORd with 62 other fields to create a redundant field. This redundant field plus the 63 data fields comprise a group. The group of fields is written to the video disk so as to maximally spatially separate adjacent fields (1686 tracks between fields). Recording occurs via an optical master disc. Stamped replications (video discs) are made from the master disc. Two fields occupy a 360-degree revolution (track) of the stamped video discs with 54.000 tracks on a disc side. Thus approximately 3 gigabytes are placed on a single disc side When data is read from the video disc disinterleaving occurs enroute to a field formatted RAM memory. The particular block having the desired information is identified and error-correction decoding of the desired block first occurs with generation of the Reed/Solomon syndromesfor all rows and columns. Nonzero syndromes indicate error. Starting with the dimension (row or column) having the most nonzero syndrome values, column and row or alternatively row and column Reed/Solomon error detection and correction algorithms are employed interactively up to three times. Upon all zero check syndromes being encountered, either before or after the Reed/Solomon iterations, auxiliary check syndromes derived from the corrected block data are examined for a zero value, which if achieved renders the block immediately available without processing adjacent blocks. Upon either the Reed/Solomon iterations to the third level occurring with nonzero syndromes still remaining (uncorrectable error) or remaining errors detected by the auxiliary check syndromes (indicating miscorrection), the Reed/Solomon algorithm is applied from the field or z-axis dimension. One or two entire blocks can be corrected by this step. If more than two blocks are not capable of regeneration, all fields of a group (spaced every 843rd track on the optical disc), save the field containing error are block level processed, field level processed and XORd to a field sized RAM to regenerate the defective field.

85 citations


Patent
18 Sep 1984
TL;DR: In this article, a shared encoder/decoder circuit for use with a Reed-Solomon coding scheme of an optical disk storage system is presented. But the same circuitry is shared for performing the encoding and decoding functions.
Abstract: A shared encoder/decoder circuit for use with a Reed-Solomon coding scheme of an optical disk storage system. The optical disk system includes a drive adapted to permanently store data on a removable platter. Prior to recording a data byte on the platter, the data is encoded with a Reed-Solomon code. When the data is read from the disk, it is decoded and error correction syndromes are generated. The same circuitry is shared for performing the encoding and decoding functions. This circuitry includes independent sets of a RAM, coupled to one input of an exclusive OR (modulo two sum) adding circuit. The output of the adding circuit is fed back to an input to the RAM. Two multiplier circuits are coupled to the output of the RAM. A product of one is tied to one input of the modulo two addition circuit. The product of the other is combined with similar products from other sets, and the resulting combination signal is selectively connected to the other input of the modulo two addition circuit, along with data to be recorded on the platter, or data read from the platter.

83 citations


Journal ArticleDOI
TL;DR: The construction is used to establish that the number of nonequivalent (perfect) binary single error correcting codes of length n is at least at least $2^{2^{cn} } $, for some constant $c < 1$.
Abstract: A product construction for binary error correcting codes is presented. Given perfect binary single error correcting codes of length n and m, one can construct perfect binary single error correcting codes of length $nm + n + m$. Among other things, the construction is used to establish that the number of nonequivalent (perfect) binary single error correcting codes of length n is at least $2^{2^{cn} } $, for some constant $c < 1$.

Patent
07 Dec 1984
TL;DR: In this article, a method for improving reception of a data word to be sent from an origination station to a destination station comprises generating and storing error correction functions for a message word including the data word.
Abstract: A method for improving reception of a data word to be sent from an origination station to a destination station comprises generating and storing error correction functions for a message word including the data word. Error correction functions are transmitted only if the message word is invalidly received thus offering improved performance over a conventional retry scheme. Interleaving reduces susceptibility to burst noise and altering carrier frequency for retransmissions minimizes effects of noise. The method is especially useful in a system comprising a central receiver and a plurality of physically separated remote transmitters wherein electrical path quality between receiver and transmitters may independently randomly vary.

Journal ArticleDOI
TL;DR: The relations between the word error probability and the decoding algorithms for block codes are reviewed and a simple approximation is derived for the information-bit error rate in terms of the channel-symbol error probability.
Abstract: The relations between the word error probability and the decoding algorithms for block codes are reviewed. A simple approximation that does not depend upon the code weight structure or the decoding details is derived for the information-bit error rate in terms of the channel-symbol error probability.

Journal ArticleDOI
TL;DR: In this paper, the authors focus on the time interval between the occurrence of an error and the detection of that error, i.e., the delay between the error occurrence and the error detection.
Abstract: Conventionally, reliability analyses either assume that a fault/error is detected immediately as it occurs, or ignore damage caused by imperfect detection mechanisms and error latency, namely, the time interval between the occurrence of an error and the detection of that error.

Patent
31 Oct 1984
TL;DR: In this article, the parity bits are used to determine whether a data word is correct and then the memory-control circuit (30) corrects the parity bit before storing the corresponding error-correction code in memory.
Abstract: In a data processing system, a memory (32) consists of data words and associated error-correction codes that are independently accessible; it is possible simultaneously to read a data word and write its associated error-correction code. This allows a memory-control circuit (30) immediately to store in the memory (32) a data word sent by a processor (10) while it is concurrently in the process of generating the error-correction code for that data word. The result is that the memory-control circuit (30) can subsequently fetch the newly stored data word before storage of its associated error-correction code is complete. This reduces delays involved in error-correction-code generation. The data word includes not only non-redundant information but also parity bits that both the processor (10) and the memory-control circuit (30) employ to determine whether a data word is correct. If the memory-control circuitry (30) determines that a word that it has forwarded to the processor (10) is incorrect, it immediately fetches the corresponding error-correction code and corrects the location in memory. Then, when the processor (10) finds that the parity is incorrect in the data word, it repeats its request for the data word in question, which the memory-control circuit (30) has corrected in the memory (32).

Patent
18 Sep 1984
TL;DR: In this article, a self-checking shared encoder/decoder circuit for a Reed-Solomon coding scheme of an optical disk storage system was proposed, where the same circuitry is shared for performing the encoding and decoding functions.
Abstract: A self-checking shared encoder/decoder circuit for use with a Reed-Solomon coding scheme of an optical disk storage system. The optical disk system includes a drive adapted to permanently store data on a removable platter. Prior to recording a data byte on the platter, the data is encoded with a Reed-Solomon code. When the data is read from the disk, it is decoded and error correction syndromes are generated. A plurality of syndrome buffer registers are provided in order to allow several of the error correction functions to be carried out in parallel. Syndromes that are detected to comprise all zeros are used to simplify the error correction processes beyond the normal processes used. The same circuitry is shared for performing the encoding and decoding functions. This circuitry includes independent sets of a RAM, coupled to one input of an exclusive OR (modulo two sum) adding circuit. The output of the adding circuit is fed back to an input of the RAM. Two multiplier circuits are coupled to the output of the RAM. A product of one is tied to one input of the modulo two addition circuit. The product of the other is combined with similar products from other sets, and the resulting combination signal is selectively connected to the other input of the modulo two addition circuit, along with data to be recorded on the platter, or data read from the platter.

Patent
22 Feb 1984
TL;DR: In this paper, the error detection check bits are included in the entire message transmitted by the base station to provide additional protection against falsing in POCSAG-based paging systems.
Abstract: In digitally encoded data transmission systems such as paging systems using a code word format, such as POCSAG, each code word includes a number of bits collectively termed the cyclic redundancy check bits. In a paging receiver the cyclic redundancy check bits are used to determine if there are errors in the received message code words. If an error is detected then one bit random error correction is generally applied because it has a more acceptable falsing rate compared to say two bit random error correction or four bit burst error correction. However a less acceptable falsing rate correction technique, such as four bit burst error correction, can be given if additional protection against falsing is provided. The additional protection comprises error detection check bits which are included in the entire message transmitted by the base station. At the receiver any errors in the message code words are subjected to four bit burst error correction and thereafter the entire "corrected" message is subjected to a further check using the error detection check bits. Whether or not error detection check bits have been included in the message is indicated by preconditioning the message, for example by using predetermined ones of the plurality of addresses allocated to each pager for different purposes. If error detection check bits have not been included a more acceptable falsing rate correction technique is applied.

Journal ArticleDOI
TL;DR: Modified Berger codes are defined in this correspondence in terms of the number of check bits and the cost of checkers, and their error detection ability is slightly lower, although these codes can detect most unidirectional errors.
Abstract: Modified Berger codes are defined in this correspondence. They are less expensive than the ordinary Berger codes in terms of the number of check bits and the cost of checkers. As a tradeoff, their error detection ability is slightly lower, although these codes can detect most unidirectional errors.

Journal ArticleDOI
01 Jan 1984

Patent
26 Apr 1984
TL;DR: In this article, an encoding method for error correction of digital information data is provided, which comprises the steps of arranging the digital data in a plurality of blocks each including a plurality-of-symbolic symbols, and generating first redundancy data from first respective groups of digital data constituting symbols which exist in at least two blocks in a first direction.
Abstract: An encoding method for error correction of digital information data is provided. The encoding method comprises the steps of arranging the digital information data in a plurality of blocks each including a plurality of symbols, and generating first redundacy data from first respective groups of digital information data constituting symbols which exist in at least two blocks in a first direction. Second redundancy data is generated from second respective groups of digital information data constituting symbols which are included in the plurality of blocks in a second direction. First code sequences are formed for first error detection from the first digital information data groups and the first redundancy data, and second code sequences are formed for second error detection from the second digital information data group and the second redundancy code. Blocks including at least one of the digital information data and the first redundancy data are transmitted, and blocks including the second redundancy data are also transmitted.

Patent
Hiroo Okamoto1, Masaharu Kobayashi1, Hiroyuki Kimura1, Takaharu Noguchi1, Takao Arai1 
31 Oct 1984
TL;DR: In this paper, error detection for first code blocks and error correction for S2 words at unknown locations and E flagged word erasures, where d1 is a Hamming distance and S2 and E satisfy a relation of 2S2+E≦d1-1, are parallely or sequentially effected, and a combination of S 2 and E having a high correction capability and a low probability of miscorrection is selected from a plurality of correction results of error locations and the numbers of flags added at the first decoding, and the word errors are corrected based on the
Abstract: Error correction of digital signals is suited for codes having error detection and correction words, such as doubly-encoded Reed-Solomon code. In a first decoding, at least error detection is effected and flags indicating decoding conditions are added. In a second decoding, error detection for first code blocks and error correction for S2 words at unknown locations and E flagged word erasures, where d1 is a Hamming distance and S2 and E satisfy a relation of 2S2+E≦d1-1, are parallely or sequentially effected, and a combination of S2 and E having a high correction capability and a low probability of miscorrection is selected from a plurality of correction results of error locations and the numbers of flags added at the first decoding, and the word errors are corrected based on the selected combination.

Patent
21 Aug 1984
TL;DR: In this paper, a system for through checking the accuracy of generation of the error correction codes and decoding of error correction code is described, where a data word parity signal is generated for storage with the associated data word and its associated check bit.
Abstract: For use with a digital memory system that generates error correction code signals for storage with associated data words and for correction of detected error(s) in the associated data words when accessed, a system for through checking the accuracy of generation of the error correction codes and the decoding of error correction code is described. A data word parity signal is generated for storage with the associated data word and its associated check bit. When a data word is accessed, the read data word and its associated check bits are applied to error correction circuitry that results in a determination of whether or not any bits of the read data word are in error. Correction circuitry corrects those error in the read data word that are correctable. The corrected read data word is applied to a parity generator circuit that generates that parity of the corrected read data word. A comparison circuit compares the word parity calculated for the corrected read data word. Comparison indicates that the error correction system and through check system functioned properly, and failure of comparison indicates an error occurred in the throughput of the data word.

Journal ArticleDOI
TL;DR: The letter proposes a continuous ARQ scheme, to be used under high error rate conditions, that preserves the ordering of the data blocks and yields a better throughput efficiency than some known comparable schemes.
Abstract: The letter proposes a continuous ARQ scheme, to be used under high error rate conditions. The scheme preserves the ordering of the data blocks and yields a better throughput efficiency—especially for channels with large round-trip delay—than some known comparable schemes, for all block error probabilities larger than 50%.

Journal ArticleDOI
TL;DR: This correspondence presents a new class of odd-weight-column SEC-DED-SbED codes for b = 4, where r is the number of check bits and [ ] denotes the ceiling or next largest integer.
Abstract: Error correcting codes are widely used in memory systems to increase reliability. Especially in a memory systern that uses byte-organized memory chips, which each contain b (≫1) output bits, a single chip failure is likely to affect many bits within a byte. Single-bit error correcting-double bit error detecting-single b-bit byte error detecting codes (SEC-DED-SbED codes) are suitable for increasing the reliability of memory system. This correspondence presents a new class of odd-weight-column SEC-DED-SbED codes for b = 4. The code length is 2r-1 - 2[r/2], where r is the number of check bits and [ ] denotes the ceiling or next largest integer. The proposed SEC-DED-S4ED codes are the best-known codes.

Patent
Hidehito Aoyagi1, Botaro Hirosaki1
24 Aug 1984
TL;DR: In this article, an error correction mechanism is also provided for correcting errors of the received data in at least any one channel, and a comparator associated with each channel is provided to deliver a first signal when the level of the data in the associated channel has been reduced below a predetermined first threshold to indicate a level reduced channel.
Abstract: The fading protection system protects against fading selectively occuring in a specific channel of a plural data transmission system. An equalizer is provided in each channel and adapted to equalize received data. An error correction mechanism is also provided for correcting errors of the received data in at least any one channel. A comparator associated with each channel is provided to deliver a first signal when the level of the received data in the associated channel has been reduced below a predetermined first threshold to indicate a level reduced channel. A controller operates in response to the first signal so as to deliver, as reference data, the correct data, after correction by the error correcting mechanism, to the equalizer provided in the level reduced channel. The controller also effects the supervised learning operation for correcting a coefficient of the equalizer in the level reduced channel so as to reduce the difference between the reference data and the output from the equalizer in the level reduced channel.

Patent
27 Dec 1984
TL;DR: In this article, an image processing system converts an image into a compressed base image and successive levels of error correction data so that an output of the image may be provided with any desired level of resolution (up to that of the input) with further levels of resolution obtained through predictive techniques.
Abstract: An image processing system to allow communication with input and output devices having varying resolutions. An image processing system converts an image into a compressed base image and successive levels of error correction data so that an output of the image may be provided with any desired level of resolution (up to that of the input) with further levels of resolution obtained through predictive techniques. Advantageously, the error coding data is arithmetically coded.

Journal ArticleDOI
H. Ma1, M. Poole
TL;DR: This paper provides performance analyses of a broad spectrum of error-correcting codes in an antijam communication system under worst-case partial-band noise jamming conditions and demonstrates the coding advantages available for systems operating with and without frequency diversity.
Abstract: This paper provides performance analyses of a broad spectrum of error-correcting codes in an antijam communication system under worst-case partial-band noise jamming conditions. These analyses demonstrate the coding advantages available for systems operating with and without frequency diversity. Utilizing both the exact approach (where possible) and upper-bounding approaches (Chernoff and union bounds), the decoded bit error rates for typical error-correcting codes (binary and M -ary, block and convolutional) have been obtained, and these codes have been compared according to the E_{b}/N_{0} required to achieve a bit error rate of 10-5. The best performance is achieved with the use of M -ary signaling and optimum diversity with M -ary codes, such as Reed-Solomon block codes, dual- k convolutional codes, convolutional orthogonal codes, or concatenated codes.

Patent
15 Jun 1984
TL;DR: In this article, a method of recording a digital data signal, such as an audio PCM signal, onto a recording medium in the lon-gitudinal direction thereof, together with an apparatus which is suitable for this recording method is presented.
Abstract: A method of recording a digital data signal, such as an audio PCM signal, onto a recording medium in the lon­gitudinal direction thereof, together with an apparatus which is suitable for this recording method. Even-­numbered words and odd-numbered words in a digital data signal are recorded on a first track group and a second track group, respectively, which are separated from each other in the widthwise direction of a recording medium, to prevent a series of words becoming error words because of, for example, a flaw in the recording medium in the longitudinal direction thereof. The data format is chang­ed at the input and output of a recording encoder to enable an error correction code and a recording circuit to be used in common for digital tape recorders which have different numbers of tracks, e.g., n tracks and 2n tracks. When an error correction code is recorded in such a manner that one word in the digital data signal is divided into a plurality of symbols which are formed into an error correction code, a plurality of symbols of the same word are recorded at a position at which error correlation is strong, making effective use of the error correction capacity of the error correction code.

Patent
15 Feb 1984
TL;DR: A method and processing matrix for detection and correction of errors in coded data based on determining the error location and error evaluator polynomials using the relationship defined by the key equation is presented in this article.
Abstract: A method and processing matrix for detection and correction of errors in coded data based on determining the error location and error evaluator polynomials using the relationship defined by the key equation. A systolic processor is disclosed which utilizes pipelining and a regular, parallel structure based on a derived algorithm for solving the key equation.

Patent
26 Sep 1984
TL;DR: In this article, a block of data is written at three-dimensional addresses in a memory in a predetermined writing order such that a 3D data arrangement is formed, and check words are added in at least two of the directions as error detecting or error correcting codes to thereby form an extended threedimensional data arrangement.
Abstract: A data transmission method in which both random errors and burst errors in data transmission are correctable. A block of data is written at three-dimensional addresses in a memory in a predetermined writing order such that a three-dimensional data arrangement is formed. Check words are added in at least two of the directions as error detecting or error correcting codes to thereby form an extended three-dimensional data arrangement. The data is then read out of the extended three-dimensional data arrangement in a predetermined reading order and transmitted as data arranged one-dimensionally. On the data receiving side, the data including the check words is written into a memory in the same order as the data transmitting side to form a three-dimensional data arrangement therein, and then read out in the same order as the data writing order on the data transmitting side. The data thus read is subjected to error correction as required.