Showing papers on "Etching (microfabrication) published in 1969"

Electromigration failure modes in aluminum metallization for semiconductor devices

Abstract: Two wear-out type failure modes involving aluminum metallization for semiconductor devices are described. Both modes involve mass transport by momentum exchange between conducting electrons and metal ions. The first failure mode is the formation of an electrically open circuit due to the condensation of vacancies in the aluminum to form voids. The second is the formation of etch pits into silicon by the dissolution of silicon into aluminum, and the transport of the solute ions down the aluminum conductor away from the silicon-aluminum interface by electron wind forces. The process continues until an etch pit grows into the silicon to a depth sufficient to short out an underlying junction.

Gas plasma vapor etching process

Abstract: Gas plasma vapor etching process utilized for removing portions of material from a semiconductor structure for a number of purposes including polishing and cleaning of the silicon wafers, finding pin holes in an insulating layer covering the semiconductor wafer and forming scribe lines in the wafer to thereafter permit the wafer to be mechanically broken into dice without any substantial damage to the dice

Method for epitactic precipitation of silicon at low temperatures

Abstract: A method for producing highly pure, monocrystalline silicon layers, with or without dopant additions, upon a wafer shaped substrate body, which comprises thermal dissociating a gaseous silane compound, and by precipitating silicon upon a heated substrate body located in a reaction chamber. The crystalline structure of the silicon body is exposed e.g. by etching and its surface is flooded by the reaction gas. The silane compound is a dihalogen silane of formula SiH2X2, wherein X is chlorine, bromine, or iodine. The thermal dissociation is effected by heating the substrate body at low temperatures, preferably within a temperature range between 600* and 1,000* C.

The influence of crystal orientation on silicon semiconductor processing

Abstract: Silicon crystallographic orientation effects on semiconductor processing from single crystal growth through completed devices or circuits have been studied. The preferred octahedral crystal habit of silicon provides for stable crystal growth on the {111} plane, but the other low-index planes, {110} and {100}, are becoming more commonly used, in spite of greater difficulty in growth and processing of these crystals. Chemical and physical properties such as etch rates and Young's modulus are affected by orientation. The effect of crystal orientation on technologies such as diffusion under film (DUF), dielectric isolation, epitaxy, selective etch and epitaxial refill, and simultaneous deposition of single crystal and polycrystal silicon are presented. In addition, orientation effects on processes of oxidation, diffusion, alloying, and scribing are discussed.

Hydrogen Etching of Silicon Carbide

Abstract: The etch rate of SiC crystals with hydrogen was investigated as a function of the reaction temperature, the hydrogen flow velocity and the hydrogen partial pressure in the H2-Ar mixture. An etching reaction mechanism and calculated expressions for the etch rate have been developed based on thermodynamical considerations. The experimental results are well explained from the approximate expression at the etch rate region higher than about 3 µ/min.

Ion‐bombardment‐enhanced etching of silicon

Abstract: A method is described which permits rapid and precise selective etching of silicon crystal surfaces without protecting any part of the surface during the etch procedure. Prior to the etching process the areas to be etched are subjected to an ion‐bombardment treatment, which increases the etch rate in the bombarded surface layer compared to the etch rate of untreated silicon. Etching characteristics for silicon crystals bombarded with neon and argon are presented and shown to agree with theoretical predictions based on a simple model in which the etching characteristics are related to implantation‐produced cluster damage.

Etching fission tracks in zircons.

Abstract: A new technique has been developed whereby fission tracks can be etched in zircon with a solution of sodiuim hydroxide at 220°C. Etching time varied between 15 minutes and 5 houtrs. Colored zircon required less etching time than the colorless varieties.

Method of fabricating coaxial circuitry

Abstract: A METHOD OF FABRICATING MICROMINATURIZED COAXIAL CIRCUITRY IN WHICH LAMINATING TECHNIQUES ARE COMBINED WITH SELECTIVE ETCHING AND ELECTROFORMING TECHNIQUES TO OBTAIN A HIGH ORDER OF DIMENSIONAL PRECISION AT REASONABLE COST.

Subminiature silicon pressure transducer

Abstract: By combining spark erosion and electrochemical etching it has been found possible to fabricate solid-state microtransducers. Technology for a pressure transducer, with an epitaxial layer as the diaphragm, will be described.

A REFINED OXIDATION-STRIPPING TECHNIQUE OF THIN N-TYPE Si FILMS.

Abstract: When energetic ions are implanted in Si-crystals an anodization-peeling technique can be used as a precise tool for the determination of the ion concentration profiles, when proper precautions are taken. Anodic oxidation rates of N-type silicon in ethylene glycol solution have been studied using neutron activation analysis and it has been found that three factors, namely chemical pretreatment, illumination, and temperature seem to have the greatest influence on the anodization process and the reproducibility. Furthermore, by using a chemical posttreatment, involving evaporation of the liquid before the activity is measured, an error of less than ± 2% for an anodic voltage of 180 V has been obtained. In addition, some data on oxidation in water, and on etching of Si in hydrofluoric acid are presented.

Process for wafer fabrication of high blocking voltage silicon elements

Abstract: A silicon wafer provided with at least one voltage-blocking junction is strengthened by epitaxially depositing silicon onto one major surface. The wafer is then etched to form grooved surfaces intersecting the junction. A passivation layer is deposited and fast diffusing impurities are gettered and removed. The wafer is broken into a plurality of discrete, separately useable silicon elements.

Dielectric isolated integrated circuit substrate processes

Abstract: Dielectric isolation has proven effective in raising inter-device breakdown voltages, lowering parasitic capacitances, and increasing resistance to radiation damage. The fabrication of a dielectric-isolated substrate, prior to diffusions, requires adequate control of the thickness of the epitaxial layer, of crowning and warpage, and of a necessarily smooth, damage-free surface. The mere juxtaposition of three or more layers of different materials, even before diffusion-induced strains, creates special problems because of coefficient-of-expansion mismatches. In addition, the substrates must pass through subsequent diffusion cycles and permit the fabrication of transistors with characteristics as good as (or better than) those made on p-n junction isolated substrates. There are three major methods of using silicon dioxide as a dielectric to separate active areas of an integrated circuit: 1) shape-back to the channels of a wafer which has had channels etched out and filled with polycrystalline silicon; 2) etch out and fill in with single crystal on an n+wafer which has already had isolation moats created; and 3) growth of polycrystalline silicon prior to etching the isolating channels. This paper describes and compares these methods.

Novel etchant and process for etching thin metal films

Abstract: A composition for etching thin films of metal, such as chromium or molybdenum, comprising alkaline metal salts of weak inorganic acids which yield solutions having a pH in the range of 12 to 13.5, e.g. sodium or potassium-meta or orthosilicates or sodium orthophosphate, and oxidizing agents active in alkaline solutions, such as potassium permanganate or sodium ferricyanide. Also, the method of selectively etching away portions of such metal films by masking said films with positive alkali-developed photoresists and treating with the etching compositions described above.

Method of producing a semiconductor or thick film device

Abstract: A METHOD OF PRODUCING A SEMICONDUCTOR OR THICK FILM DEVICE COMPRISES FORMING A LAYER OF ETCHING RESISTANT, TEMPERATURE RESISTANT AND LIGHT INSENSITIVE PLASTICS MATERIAL ON A CARRIER BODY, SUCH AS AN INSULATING MATERIAL OR SEMICONDUCTOR BODY AND REMOVING PREDETERMINED AREAS OF THE PLASTICS LAYER BY MEANS OF A CONTROLLED ELECTRON BEAM. THE AREAS OF THE CARRIER BODY FROM WHICH THE PLASTICS MATERIAL HAS BEEN REMOVED CAN BE USED FOR THE REMOVAL OF FURTHER MATERIAL, DEPOSITING FURTHER MATERIAL OR THE INTRODUCTION OF FURTHER MATERIAL.

Method of producing air-isolated integrated circuits

Abstract: Islands of dielectrically isolated monocrystalline silicon, fabricated in a polycrystalline base, are first produced. Device fabrication and beam lead interconnection follow. Thereafter the planar top surface is covered with an etch-resistant wax and the polycrystalline base is removed by etching. In another embodiment, SiO2 is grown on a grooved, monocrystalline silicon slice, and polycrystalline silicon is deposited thereover. The slice is then lapped down on the top side so that the polycrystalline silicon and SiO2 form barriers. Second side is lapped after devices are fabricated and after beam leads are formed. Active devices and beam leads are fabricated on one surface, and the polycrystalline material is lapped and etched away from the back. In either case, the remaining structure is an air-isolated beam lead device.

Low temperature silicon etch

Abstract: A MECHANICALLY POLISHED SILICON WAFER IS ETECHED TO REMOVE SURFACE DAMAGED MATERIAL AND GIVE A SMOOTH SURFACE BY ETCHING AT A TEMPERATURE OF FROM ABOUT 800 TO 1050*C. IN A GAS MIXTURE CONSISTING OF A CARRIER GAS OF H2, HE OR A MIXTURE THEREOF, A SMALL CONCENTRATION OF A GAS REACTIVE WITH SIO2 SUCH AS HF, CIF3 OR BRF5 AND A SMALL CONCENTRATION OF A GAS REACTIVE SILICON SUCH AS HBR, HI, HCL, CL2, BR2, OR I2.

Apparatus and method for sputter etching

Abstract: The object to be sputter etched is excited in a reduced atmosphere of inert gas by the application of an RF potential across a pair of electrodes, one of which supports the object and is capacitively coupled to the RF source. The improvement is a means to catch and retain material removed by the sputtering operation.

Method for etching thin film materials by direct cathodic back sputtering

Abstract: Thin layers of material including dielectric films are etched or cleaned by placing them in a low pressure gas ambient, forming a plasma in the ambient, and establishing a periodic voltage between the layers and the plasma. One important application of the process is the formation of metal silicide contacts through small windows in a dielectric layer protecting the silicon surface. In one application, the metal is sputtered onto the exposed silicon at the same time that the surface is subjected to ion bombardment. The sputtering and etching rates are adjusted so that some of the sputtered metal reacts with the silicon upon impact and the unreacted metal is etched away.

Reaction of Second-phase Constituents in Aluminium During Etching in Sodium Hydroxide Based Solutions

Abstract: The behaviour has been studied of second-phase constituents in alloys based on super-purity aluminium (99–99% purity) during etching in solutions based on sodium hydroxide. Firstly the reactions of...

Etching composition indication

Abstract: In the etching through a protective glass coating to expose an underlying metal, overetching is prevented by adding a polyhydric alcohol, for example glycerin, to a glass etchant, which causes a color change on a metal, for example aluminum or molybdenum, indicating that etching through the glass coating has been completed.

Method for isolating semiconductor devices from a wafer of semiconducting material

Abstract: AN ARRAY OF DEVICES IS FIRST FORMED IN A SILICON WAFER. A PROTECTIVE LAYER OF SILICON NITRIDE IS DEPOSITED ON THE SURFACE OF THE WAFER, AND A GLASS HANDLE BODY HAVING A THERMAL EXPANSION COEFFICIENT CLOSELY MATCHING THAT OF SILICON IS SEALED TO THE SILICON NITRIDE LAYER. THAT PORTION OF THE WAFER BETWEEN ADJACENT DEVICES IS ETCHED AWAY, AND A BODY OF A SOFTENED GLASS WHICH HAS A LIKE EXPANSION COEFFICIENT, BUT IS LESS REFRACTORY THAN THE GLASS HANDLE BODY, IS HOT-PRESSED INTO THE ARRAY OF ISOLATED DEVICES. THE HANDLE BODY IS THEN REMOVED BY ETCHING. D R A W I N G

Method of making a semiconductor article and the article produced thereby

Abstract: A portion of the surface of a body of single crystalline silicon is etched to provide a wall which is substantially perpendicular to the surface of the body The body is formed with the surface oriented in a (110) crystallographic plane The surface is then etched with a crystallographically selective etching solution, such as a hot caustic solution, along a (111) crystallographic plane which extends perpendicularly to the (110) oriented surface

Capacitors and methods for their manufacture

Abstract: 1,149,569. Capacitors. MINISTER OF TECHNOLOGY. 31 Aug., 1967 [1 Sept., 1966], No. 39007/66. Heading H1M. A capacitor comprises a pair of coplanar electrodes 1, 2 on a dielectric substrate 3, the electrodes having interdigitated projections 5, 6, 7 and 8, and a dielectric overlayer which fills the space 4 between the projections (Figs. 3, 4, not shown), the useful capacitance being derived from the proximity of the edges of the projections. The capacitance may be further increased by another parallel connected pair of electrodes on the overlayer (Fig. 5, not shown). The substrate and overlayer dielectric may be glass, ceramic, alumina, barium titanate, lead titanate zirconate or silicon monoxide and may be selected so that its change of dielectric constant with temperature compensates for its thermal expansion. To form the electrodes a single conductive layer of, e.g. tantalum may be applied and divided by a meandering slot by electron beam treatment or a masking and etching process. Alternatively the electrodes may be printed separately. The capacitance may be trimmed to a desired value by electron beam treatment, or anodizing, or etching.

Dicing of semiconductors

Abstract: In the manufacture of semiconductors by forming a large number of devices on one wafer, protecting the individual devices by wax masks and then subjecting the wafer to an etching acid to separate the devices, apparatus is used for separating the wafers comprising a tray on which the wafer is placed. Means is provided for circulating an etching acid in a path including the tray, and in this path there is means for controlling the temperature of the acid.

Separating and maintaining original dice position in a wafer

Abstract: A wafer of silicon material containing semiconductor devices on its front side has an oxide coating on its back side. The back side is masked and aligned in conformity with the devices on the front side. The oxide is selectively etched and the remaining oxide serves as a mask for etching through the semiconductor material. The devices are retained in relative position throughout the separation steps.