Showing papers on "Etching (microfabrication) published in 1978"

Plasma etching of Si and SiO2—The effect of oxygen additions to CF4 plasmas

Abstract: The plasma etching of silicon and silicon dioxide in CF4‐O2 mixtures has been studied as a function of feed‐gas composition in a 13.56‐MHz plasmagenerated in a radial‐flow reactor at 200 W and 0.35 Torr. Conversion of CF4 to stable products (CO, CO2, COF2, and SiF4) and the concentration of free F atoms ([F]) in the plasma were measured using a number of different diagnostics. The rate of etching, the concentration of F atoms, and the intensity of emission from electronically excited F atoms (3s 2 P–3p 2 P° transition at 703.7 nm) each exhibit a maximum value as a function of feed‐gas composition ([O2]); these respective maxima occur at distinct oxygen concentrations. For SiO2, the variation in etching rate with [O2] is accounted for by a proportional variation in [F], the active etchant. The etching of silicon also occurs by a reaction with F atoms, but oxygen competes with F for active surface sites. A quantitative model which takes oxygen adsorption into account is used to relate the etch rate to [F]. The initial increase of [F] with [O2] is accounted for by a sequence of reactions initiating with the production of CF3 radicals by electron impact and followed by a reaction of CF3 with oxygen. When [O2] exceeds ∼23% (under the present discharge conditions), [F] decreases due, probably, to a decrease in electron energy with an increase of oxygen in the feed gas.

Fabrication of novel three-dimensional microstructures by the anisotropic etching of

Abstract: The anisotropic etching of single crystal silicon oil ((loo) and (110) orientation in a solution of pyrocatechol, ethylene di:nnine, and water is reviewed and the fabrication of three novel types of nicro- structures is described in detail. Controlled etching of Si, whicpi is re- quired to fabricate devices with a predictable geometry depends on : an accurately oriented, defect-free substrate, a well-defined and ali.ped pattern geometry, and rigorously clean etching conditions. Chnven- tional IC processing methods were used to fabricate: 1) a high-precision circular orifice in a thin pfSi membrane for use as an ink jet ncmle, 2) a multisocket miniature electrical connector with octahedral 'c wities suitable for cryogenic applications, and 3) multichannel anri;ys in (100) and (110) Si useful in various applications, eg., charge elecdttodes, physical masks, and optical devices. To make some of these strcwlures, a novel bonding technique to fuse silicon wafers with phosphalsilicate glass films was developed.

Micromechanical display logic and array

Abstract: A display device, addressing circuitry, and semiconductor control logic are all portions of an integrated structure formed by thin film technology on a single silicon wafer. The display comprises a thin film micromechanical electrostatic form of light reflective display formed by depositing thin films upon a silicon wafer and selectively etching to form metal-amorphous oxide micromechanical leaves deflected by applying potential thereto to provide electrostatic deflection. MOSFET devices are also formed upon the silicon wafer in juxtaposition with a plurality of micromechanical display elements. Addressing circuitry is connected to the MOSFET devices.

Profile control by reactive sputter etching

Abstract: Reactive sputter etching in fluorocarbon gases (i.e. CF4, CHF3) not only results in a large increase of the etch rates, but it can also be used for a high fidelity pattern transfer from patterns delineated in positive photoresist into underlaying substrates (i.e. Si, SiO2, Si3N4). Square wave gratings with micron and submicron periodicities and etch depths of up to 3 μm have been etched. A relatively large etch selectivity of SiO2 over Si has been observed (etch rate ratio=15:1). Reactive sputter etching is primarily a chemical process due to highly reactive species produced on the substrate surface by an ion–molecule reaction between ions from the plasma and neutral gas molecules impinging onto the substrate surface.

Device fabrication by plasma etching

Abstract: High density fine-line integrated structure fabrication is expedited by use of plasma etching systems which assure straight vertical walls (absence of undercutting). Critical to the sytems is choice of appropriate plasma chemistry. Appropriate systems are characterized by inclusion of recombination centers, as well as active etchant species. Recombination centers which effectively terminate etchant species lifetime in the immediate vicinity of resist walls afford means for controlling etching anisotropy. Use is foreseen in large scale integrated circuitry (LSI) and is expected to be of particular interest for extremely fine design rules, i.e., in Very Large Scale Integrated circuitry.

In 1-x Ga x As y P 1-y /InP DH lasers fabricated on InP

Abstract: In 1-x Ga x As y P 1-y /InP double heterostructure (DH) laser diodes with emission wavelengths of 1.25-1.35\mu m at room temperature were fabricated on

Method of cleaving semiconductor diode laser wafers

Abstract: Thick double heterostructure (Al,Ga)As wafers comprising layers of gallium arsenide and gallium aluminum arsenide on a metallized n-GaAs substrate are separated into individual devices for use as diode lasers. In contrast to prior art techniques employed with thinner wafers of mechanically cleaving the wafer in mutually orthogonal directions, the wafer is first separated into bars of diodes by a process which comprises (a) forming channels of substantially parallel sidewalls about 1 to 4 mils deep into the surface of the n-GaAs substrate (b) etching into the n-GaAs substrate with an anisotropic etchant to a depth sufficient to form V-grooves in the bottom of the channels and (c) mechanically cleaving into bars of diodes. The cleaving may be done by prior art techniques using a knife, razor blade or tweezer edge or by attaching the side of the wafer opposite to the V-grooves to a flexible adhesive tape and rolling the assembly in a manner such as over a tool of small radius. The diode bars may then, following passivation, be further cleaved into individual diodes by the prior art technique of mechanically scribing and cleaving. Processing in accordance with the invention results in good length definition and uniformity, high device yields and low density of striations on laser facets. The inventive process permits handling of thicker wafers on the order of 6 to 10 mils or so, which are cleaved only with great difficulty by prior art techniques. Such thicker wafers are less susceptible to breaking during handling and permit fabrication of shorter diode (cavity) length, which in turn is related to lower threshold current for device operation.

Process and material for manufacturing semiconductor devices

Abstract: A process step and material for use in the manufacture of semiconductor devices. To facilitate the etching of unmasked silicon dioxide, silicon nitride, silicon monoxide, bare silicon layers, or various refractory metals on preselected portions of a semiconductor slice, the material is exposed to a low pressure RF generated "cold" plasma (under 325° C.) produced from a homogeneous gaseous binary mixture of oxygen and a halocarbon. The halocarbon is preferably a gas having one carbon atom per molecule and is preferably fully fluorine-substituted.

Mechanism of silicon etching by a CF4 plasma

Abstract: The mechanisms for the reactive ion etching of silicon by CF4 plasma are investigated A model is proposed whereby silicon is etched by chemical reaction with free fluorine to produce a volatile species, and also by physical sputtering The chemical etching is shown to be enhanced by ion bombardment of the reacting surface This etching process, together with a model for cracking CF4 in the plasma, is evaluated by comparison to actual etch rates Experimentally, the silicon etch rate is observed to decrease with increasing silicon area, by what is called the loading effect The functional form of the loading effect, as predicted by the model, is fitted to experimental loading curves The contributions of the various etching components are separated, to yield empirical values for the enhancement of the chemical reaction by physical sputtering

Hardened photoresist master image mask process

Abstract: An improved mask fabrication process is disclosed which may be broadly applied to ion-implantation, reactive plasma etching, or the etching of semiconductor structures. The process is based upon the deposition onto an oxide coated or bare semiconductor surface, of a first photoresist layer having formed therein a plurality of windows and which is hardened by a wet chemical technique so as to have an increased resistance to dissolution in solvents. A second photoresist layer is deposited over the surface and windows of the first layer and a subplurality of windows are formed therein over selected windows in the first photoresist layer so as to selectively block a portion of the plurality of windows in the first layer. This composite mask invention may then be employed to carry out an ion-implantation step, wet etching step or reactive plasma etching step on the oxide or semiconductor surface exposed through composite windows. The second layer of photoresist may then be removed and a substitute photoresist layer may be deposited on the surface and windows of the first, hardened photoresist layer and a different subplurality of windows in the substitute layer may be selectively formed over selected windows in the hardened photoresist layer, thereby selectively blocking a different combination of windows in the first, hardened layer.

Method of forming thin film interconnection systems

Abstract: A method for forming thin film interconnection patterns atop substrates, particularly semiconductor substrates. It features the use of the passivation layer itself, typically glass, as a stable masking material to etch the conductive lines. Conversely, the metal conductor is used as a stable mask in etching the glass to form via holes. The process provides a practical resist system which is compatible with reactive ion etching or other dry etching process.

Very Thin Silicon Nitride Films Grown by Direct Thermal Reaction with Nitrogen

Abstract: Very thin uniform silicon nitride films less than 100A have been obtained on silicon wafers by direct thermal reaction with nitrogen at temperatures ranging from 1200° to 1300°C. Small amounts of water or oxygen in reaction mixture caused vapor etching which gave rise to local crystallization. By eliminating both from the reaction ambient to less than 1 ppm, amorphous silicon nitride films can be deposited. These films have been found to have properties similar to those of CVD by investigations of Auger electron spectroscopy, infrared spectroscopy, and ellipsometry. Remarkable masking effects of the films against oxidation and phosphorus diffusion have been found.

A New Etching Solution System, H 3 PO 4 ‐ H 2 O 2 ‐ H 2 O , for GaAs and Its Kinetics

Abstract: A new solution system consisting of , , and was found useful for etching wafers. This solution system can be divided into four regions a–d, according to etching characteristics. The boundaries between the regions are given by a mole ratio of to of about 2.3 and a mole fraction of of about 0.9 at room temperature. Rate‐limiting processes are: a, adsorption of (, ); b, diffusion of (, ); c, dissolution of oxidized products (, ); and d, adsorption of (,). Solutions in region a have a reproducible etching rate of 0.01–0.1 μm/min, which is useful for MESFET processing. Crystallographic etching is also available with solutions in region c.

Dry etching method

Abstract: A radio frequency and a static electric field are superposedly applied to a low pressure gas to generate a gaseous plasma and to drive ions of selected polarity in a predetermined direction. The processing chamber is pre-evacuated to a sufficiently high vacuum, and an etching gas is introduced into the chamber to be rendered to a low pressure at which the mean free path of the ions is sufficiently long. The pressure of the etching gas may range from the order of 10 -2 Torr to several Torr for etching silicon, using a silicon oxide as a mask material. This method improves the treating accuracy, especially minimizes the amount of side etch, as compared with the conventional plasma etching, and reduces the surface damage when compared with the known ion beam etching.

Reactive ion etching of aluminum and aluminum alloys in an rf plasma containing halogen species

Abstract: An etching method capable of producing vertical‐walled high‐resolution patterns in aluminum and aluminum alloy films is described. The process consists of rf sputter etching in a plasma containing ion species, which react with the metal to form volatile or easily sputtered compounds. The presence of reactive species greatly enhances the etch rate, while the electric field maintains the directionality inherent in the sputtering process. Halogen ion species, as obtained in rf plasmas containing a partial pressure of Cl2, Br2, HCl, HBr, or CCl4, were used to produce reactive ion etching of Al. The etch rate in a CCl4 plasma at a power input of 0.6 W/cm2 is as high as 5000 A/min. Variations in reaction rate with rf power, reactant concentration, reactant flow rate, temperature, gas pressure, batch size, and residual gas contamination are discussed. Etch rate data for various materials found suitable for masking are also presented.

Patterned multi-layer structure and manufacturing method

Abstract: A patterned multi-layer structure for a stripe filter used for a photoelectric pickup tube, comprises a protective layer preventing a substrate from being etched by reactive sputter etching and a multi-layer optical filter formed on the protective layer patterned by reactive sputter etching into a stripe pattern. The etching rate of the protective layer by an etching gas agent is not greater than that of the multi-layer filter.

Self-aligning double polycrystalline silicon etching process

Abstract: A process for fabricating a double layer polycrystalline silicon structure for a metal-oxide-semiconductor (MOS) integrated circuit. The upper polycrystalline silicon layer after being etched to form a predetermined pattern is used as a masking member for etching the lower polycrystalline silicon layer, thereby assuring alignment between the layers. A selective etchant which discriminates between the silicon layers is employed.

Method of manufacturing semiconductor devices using laser beam cutting

Abstract: A method of manufacturing semiconductor devices using laser beam cutting is disclosed in which the surface debris or pollution resulting from the laser beam cutting operation is removed by a preferential etching treatment. Since the polluting particles are of nonmonocrystalline semiconductor material, while the underlying material of the semiconductor disc is monocrystalline in nature, the polluting particles may be selectively removed in an effective manner by preferentially etching the nonmonocrystalline material of the particles with respect to the monocrystalline material of the disc. This preferential etching treatment may advantageously be carried out prior to the severing of the semiconductor disc to form the individual semiconductor devices.

Flow rate effects in plasma etching

Abstract: Experimental data concerning the dependence of plasma etching rates on the flow rate of the etching gas have been analyzed in terms of the consumption of the gas, and a simple model is proposed to explain the observed dependence. The decrease in etch rates at low flow rates is shown to be due to an inadequate supply of the etching gas; at high flow rates, etching is retarded because active species are pumped away.

Etching of MgO crystals in acids: kinetics and mechanism of dissolution

Abstract: Kinetics of etching of MgO crystals have been studied in H2SO4, HNO3 and HCl. The effects of etching time, acid concentration and temperature on the growth of hillocks, on the selective etch rate and on the rate of overall dissolution are demonstrated. It is observed that etch rates are independent of time, but are determined by the temperature and concentration of the acid. The etch rate-concentration curves show maxima which are characteristic of an acid. The values of activation energy for the processes of dissolution, selective etching and hillock growth and the corresponding frequency factors are computed. It is established that the process of dissolution in concentrated H2SO4 is diffusion controlled, while in H2SO4 with concentrations below 18 N and in HNO3 and HCl it is reaction rate controlled. The pre-exponential factor is found to be a function of acid concentration. The results are discussed from the standpoint of chemistry. A comment on the data published on MgO by previous workers is made.

Method for making a silicon mask

Abstract: In the fabrication of semiconductor integrated circuits, a method is provided for forming a self-supporting silicon mask and a further method is provided for utiliziing such a self-supporting separable silicon mask to perform various masking steps in the integrated circuit fabrication. The mask is formed by forming, at a surface of a planar silicon substrate, a silicon layer having a higher concentration of conductivity-determining impurities than the substrate beneath the layer, applying to selected portions of the other surface of the substrate an etchant which preferentially etches silicon having lower concentrations of conductivity-determining impurities to thus etch out preferentially selected portions of the substrate to form at least one recess extending through the substrate to said silicon layer, and then etching from the surface of said silicon layer opposite the substrate recess to form patterns of openings extending through the silicon layer to said substrate recess. The seperable self-supporting silicon mask thus formed is then placed on the surface of an integrated semiconductor circuit member so that the opposite surface of the silicon layer interfaces with the integrated circuit member surface. Then, the masked semiconductor member may be subjectd to any conventional integrated circuit fabrication step which alters the characteristics of the portions of said member surface exposed in said pattern of mask openings; such fabrication steps include introduction of impurities, etching as well as lift-off deposition of metallic and non-metallic patterns. Upon the completion of the step or steps, the self-supporting silicon mask is separated from the integrated circuit member.

Method of forming an integrated circuit structure with fully-enclosed air isolation

Abstract: A method for forming a fully-enclosed air isolation structure which comprises etching a pattern of cavities extending from one surface of a silicon substrate into the substrate to laterally surround and electrically isolate said plurality of substrate pockets, and then forming a first layer of silicon dioxide on said first substrate surface. Next, a planar second layer comprising silicon dioxide is formed over a second silicon substrate, after which this planar layer is fused to said silicon dioxide layer to thereby fully enclose said cavities. Then, the second silicon substrate is removed.

Process for producing uniform nozzle orifices in silicon wafers

Abstract: Nozzle plates for ink jet recording are produced by etching through silicon and like monocrystalline material wafers which frequently are non-uniform in thickness. The "100" plane surfaces of the wafers are coated with etchant masking material after which a nozzle array pattern is defined on the obverse surface and a similar, but larger and less exacting, aperture array of the same pattern is defined on the reverse surface. The silicon wafer as thus exposed is anisotropically etched from the reverse substantially through to the obverse and thereafter etched completely through the wafer from the obverse by the same anisotropic process. The lateral walls of the nozzles are substantially in the "111" plane of the wafers. The masking material is then stripped from the wafer.

Gas etching method and apparatus

Abstract: A gas etching apparatus comprising an etching gas-producing chamber; means for introducing into said chamber a mixture of a gas containing fluorine atoms and a gas containing oxygen atoms; means for activating the gas mixture received in the etching gas-producing chamber; an etching chamber provided in a region located apart from the etching gas-producing chamber and free from the electric field produced by the activating means; and an etching gas-conducting pipe means for establishing communication between the etching gas-producing chamber and etching chamber, the improvement being that the etching gas-conducting pipe means is designed to satisfy the following formula: 10sup-1 Se≦ CsubT ≦ 5×10sup2 Se where: C t = conductance (l/min) of the etching gas-conducting pipe means; Se= effective exhaust speed (l/min) in the etching chamber

CdS/InP and CdS/GaAs heterojunctions by chemical‐vapor deposition of CdS

Abstract: CdS/InP and CdS/GaAs heterojunctions were prepared by an in situ H2S/H2 etching process and H2 transport of CdS onto the InP and GaAs substrates. The etching involves a reaction of the III‐V compound surface to the corresponding sesquisulfides and simultaneous or subsequent removal by reduction in H2 gas. The etching process changes the junction characteristics considerably. The junction on p‐GaAs shows a pinning of the Fermi level at the interface approximately 0.75 eV above the GaAs valence band. The junction on n‐GaAs is Ohmic.

The Detection of Structural Defects in GaAs by Electrochemical Etching

Abstract: Two methods of anodically etching have been investigated. Subsequently they have been used to detect crystallographic defects present in bulk‐grown, single crystal material. The first method provides topographical featuring of the semiconductor anode. The selective discrimination of defects achieved via this controlled electrochemical technique is superior to that obtainable from standard chemical etchants. The second dissolution regime, in which an interfacial oxide layer is continuously present, permits smooth, featureless removal of material. Thus a simple two‐stage anodization procedure has allowed the damage characteristic of the Beilby layer to be probed. Thereafter, a total, smooth removal of this damaged surface layer permits identification of bulk crystallographic defects—dislocation structures well known in require the dissolution of only 0.5 μm. Analysis of the semiconductor electrode condition in the electrolytes used for etching has yielded model results. Such analyses have enabled the relationship between the electrical properties of the defected and the individual topography of the defects as etched to be explored.

Method for producing a single transistor storage cell

Abstract: For the production of V-MOS single transistor storage cells at the surface of a silicon crystal of first conductivity type, two adjoining zones of opposite conductivity type can first be produced by masked diffusion or implantation. Then, with the use of a correspondingly oriented etching mask, a funnel-shaped depression is produced at the semiconductor surface such that the two zones of opposite conductivity type are separated from one another but reach the surface of the silicon crystal within the funnel-shaped depression. This depression is then coated with a thin SiO 2 layer which is provided as a carrier of the gate electrode of the field effect transistor which forms the storage cell. The two zones of the opposite conductivity type, now separated, are used as a source and as a drain and also as a storage capacitance. For geometric reasons, the two zones of opposite conductivity type can only be produced one after the other with the use of corresponding doping masks. A mask is additionally required in order to produce the funnel-shaped depression. The masks must be carefully adjusted in relation to one another. In order to eliminate the need for an additional mask, one of the masks used for the production of the zones of opposite conductivity type is employed without change as an etching mask for the production of the funnel-shaped depression. The layer forming the doping mask must then, in addition to its impermeability for the doping material utilized, also be resistant against the etching compound to be utilized.

An XPS Analysis of Thermally Grown Oxide Film on GaP

Abstract: The XPS method combined with argon-ion etching has been applied in order to study the chemical depth profile of surface thermal-oxide layers on GaP(). The influence of the ion etching process on the depth profile has been studied. The deviation of the measured profile from the true one was caused mainly by the fact that atoms are not removed layer by layer by ion etching. The thermal oxide formed on GaP has been identified as GaPO4. It has been found that the width of the transition region increases as the thickness of the surface oxide layers increases. For example, when GaP() is oxidized at 700°C for 15 min, a surface oxide layer of 340 A is formed, and the transition region has a width of 175±73 A.