Showing papers on "Etching (microfabrication) published in 1986"

Wafer bonding for silicon‐on‐insulator technologies

Abstract: A silicon wafer bonding process is described in which only thermally grown oxide is present between wafer pairs. Bonding occurs after insertion into an oxidizing ambient. It is proposed the wafers are drawn into intimate contact as a result of the gaseous oxygen between them being consumed by oxidation, thus producing a partial vacuum. The proposed bonding mechanism is polymerization of silanol bonds between wafer pairs. Silicon on insulator (SOI) is produced by etching away all but a few microns of one of the bonded pair. Capacitor measurements show a 27 μs minority‐carrier lifetime and no degradation of the SOI‐insulator interface. In addition, there is negligible charge at the bonding interface making the technique attractive for three‐dimensional as well as planar SOI applications.

Dynamics of UV laser ablation of organic polymer surfaces

Abstract: A model based on a time‐dependent treatment of the ablation of organic polymer surfaces by UV laser radiation is proposed. It relates the dynamics of the etching process to the experimental parameters such as the fluence, wavelength, and the width of the laser pulse. The model is applied to poly(methyl methacrylate) and to polyimide in order to predict the etch characteristics quantitatively and to compare them systematically to the experimental results. This model accounts for a wide variety of observations such as fluence thresholds, wavelength‐dependent etch rates, ‘‘incubation’’ pulses, filtering by photofragments, fast intrapulse etching, thermal contributions, and even the influence of pulse compression so that a consistent picture of the mechanisms underlying the ablation process becomes apparent.

Excimer laser etching of polymers

Abstract: The ablative decomposition of polyimide, poly(methylmethacrylate), and TNS2 photoresist at high excimer laser (ArF and KrF) fluences (>1 J/cm2) is investigated. It is found that the mechanism of etching is both photochemical and thermal in nature at these fluences. A model, in which a thermal contribution to etching is added to the photochemical contribution derived from low fluence measurements, has been found to represent the experimental data satisfactorily. It is also shown that feature sizes as small as 0.4 μm can be delineated on polymeric materials in a self‐developing manner using 193‐nm laser pulses and contact‐printing techniques.

Film formation mechanisms in the plasma deposition of hydrogenated amorphous silicon

Abstract: By studying the step coverage of plasma‐deposited amorphous silicon and germanium on patterned substrates, we find that the film formation process under device‐quality deposition conditions has a substantial component that behaves like a surface rate‐limited chemical vapor deposition process, while conditions producing defective material are associated with a much more physical‐vapor‐deposition‐like process. An explanation involving surface reactions of SiHx radicals is proposed.

Interlayer dielectric process

Abstract: A method for producing a film over a topologically non-planar surface of a material which has a sputter etch rate which is higher in a direction parallel to the plane of the wafer than in a direction perpendicular to the plane of the wafer. Key steps in the process include first, depositing the material by plasma enhanced chemical vapor deposition while simultaneously sputter etching it. Then second, sputter etching the material. Using this two step process, a substantially conformal or sloped film is produced by repeating the steps consecutively until the desired thickness is obtained. The film can then be substantially planarized if desired, by an extended sputter etch to selectively remove material having a sloped surface rather than a flat surface, since the etch rate is higher parallel to the plane of the wafer than perpendicular to the wafer. If a thicker planar surface is desired, additional material can then be deposited by steps of simultaneous plasma chemical vapor deposition and sputter etch, or by consecutive steps of simultaneous plasma deposition and sputter etch followed by sputter etching.

Manufacture of semiconductor device

Abstract: PURPOSE:To make it possible to form a resistor or a wiring beneath an element region in a dielectric isolating structure by surrounding the entire surface of a single crystal region which is isolated with a non-single crystal silicon that is embedded in a groove formed in a semiconductor substrate with a three-layer structure of an insulating film, a conductor layer and an insulating film. CONSTITUTION:An isolating groove 12 is formed by selective etching (isotropic etching) by using KOH in a single-crystal silicon substrate 11. An insulating SiO2 film 13 is deposited on the entire surface. Then, a wiring layer 14 having the thickness of 100-1,000Angstrom is formed with conductive material (e.g., high- melting-point metal such as nickel chromium) by an evaporating method. An insulating film SiO2 film 15 is deposited again. Then a supporting layer 16 is formed by growing polycrystalline silicon. Etching is performed to a position shown with a broken line. A dielectric isolated substrate having a single crystal region 17 that is isolated with the SiO2 film 13 and the conductive layer 14 that is isolated with the insulating SiO2 films 13 and 15 can be obtained without using especially complicated steps. When the conductive layer 14 is utilized as a resistor, polycrystalline silicon whose resistivity is controlled by ion implantation can be used.

Method of making multilayer capacitor memory device

Abstract: A semiconductor device comprising a capacitor of a laminated structure and a method of manufacturing thereof, in which first conductive layer and second conductive layer of different materials or different compositions are stacked alternately with dielectric films interposed therebetween and the first conductive layers and the second conductive layers are interconnected respectively at a time by suitably combining a selective etching method and an anisotropic etching method.

Chemical etching of GaAs and InP by chlorine: The thermodynamically predicted dependence on Cl2 pressure and temperature

Abstract: This paper reports a detailed thermodynamic analysis of the GaAs/Cl and InP/Cl chemical systems, which are of interest in the technological processing of these III–V materials. The thermodynamically predicted dependence of the steady state chemical etching on both Cl2 pressure and temperature is derived assuming Langmuir free evaporation from the surface. The chemical potential data base used in this thermodynamic analysis has been checked for accuracy against all available vapor pressure measurements in the literature. The thermodynamically predicted chemical etching is compared to the etching observed in a Cl2 plasma. This approach shows promise in semiquantitative modeling of the dependence of these reactions on both the temperature and Cl2 pressure. In addition, changes in the surface morphologies resulting from plasma etching appear to be correlated with the thermodynamically predicted transitions of various compounds on the surface.

Method of fabricating a cantilever beam for a monolithic accelerometer

Abstract: A monolithic accelerometer is fabricated with an integral cantilever beam sensing element which is etched out of a silicon wafer from the back surface. A thermal silicon oxide is formed on both surfaces of a (100) silicon wafer. Silicon oxide is removed from the back surface in a pattern which defines the sides of the cantilever beam and the sides of an alignment groove. The width and orientation of the openings in the silicon oxide are selected to control the depth of etching when the wafer is subsequently etched with an anisotropic etchant. An integrated circuit is then formed on the front surface and dry etching is used to complete the groove and separate the sides of the beam from the wafer.

Reactive‐Ion Etching

Abstract: Our ability to develop and build ever smaller microelectronic devices depends strongly on the capability to generate a desired device pattern in an image layer (photoresist) by lithography and then to transfer this pattern into the layers of materials of which the device consists. In the past the pattern transfer was almost exclusively accomplished by wet etching. Chemical dissolution of a film region that had to be removed took place in a suitable solvent. Although the wet etching processes stop precisely at a chemically different underlying layer, they typically have isotropic etch characteristics, which cost the researcher control over critical lateral dimensions. Such a tradeoff is not acceptable in the manufacture of micron‐ and submicron‐scale devices, and wet, solution‐based etching techniques were replaced in the late 1970s by dry, directional etching processes using plasmas or ion beams. Figure 1 shows a plasma‐based dry etching system at IBM. In dry etching processes, surface atoms are removed v...

Solid state transducer and method of making same

Abstract: Folded cantilever structures and solid state force transducers using same are made by chemical etching of a semiconductive wafer. In the chemical etching process, an etch stop layer is provided on a wafer of semiconductive material. The etch stop layer is opened in a certain pre-determined pattern and etchant is introduced through the opening in the etch stop layer to produce substantial undercut etching of portions of the etch stop layer. The opening is patterned to define a support structure (frame) for the folded cantilever portion which is undercut. The etch is terminated such that one end of the undercut folded cantilever structure is supported from the frame and the other end terminates on a structure such as a mass that is supported from the frame by means of the folded cantilever structure.

Integrated, microminiature electric to fluidic valve

Abstract: There is disclosed herein an apparatus for converting control signals of an electrical or optical nature of any other type or signal which may be converted to a change of temperature of a fixed volume of material trapped in a chamber to flexure of a membrane forming one wall of the chamber. Typically the device is integrated onto a silicon wafer by anisotropically etching a trench into said wafer far enough that a thin wall of silicon remains as the bottom wall of the trench. In some embodiments, polyimide is used as the material for the membrane. The trench is then hermetically sealed in any one of a number of different ways and the material to be trapped is either encapsulated during the sealing process or later placed in the cavity by use of a fill hole. Typically, a resistor pattern is etched on the face of a pyrex wafer used as a top for the trench to form the cavity. When current is passed through this resistor, the material in the cavity is heated, its vapor pressure increases and expansion occurs. This causes the flexible wall to flex outward. This outward flex movement may then be used to either shut off a fluid flow path, or be sensed in some manner when using the device as a transducer. Typically, a fluid passageway having a nozzle aperture surrounded by a sealing surface is photolithographically etched into a third wafer. This third wafer is then bonded to the first wafer such that the sealing surface is adjacent to the membrane such that when expansion in the cavity occurs, the membrane flexes until it contacts the sealing surface and shuts off fluid flow through the nozzle aperture.

A planarization process for double metal mos using spin-on glass as a sacrificial layer

Abstract: A method of providing a planar or iso-planar surface to the interlevel dielectric layer between metal layers of a multilevel MOS wafer includes applying a first dielectric over the first metal layer, applying a layer of spin-on glass over the first dielectric layer, etching the spin-on glass layer in an etch process in which the rate of etch of the spin-on glass is approximately the same as the rate of etch of the first dielectric to reveal at least a portion of the first dielectric layer. A second dielectric layer is placed over the surface of the first dielectric. Vias may then be defined through the dielectric layers, and the second metal layer may be applied over the relatively smooth surface of the second dielectric layer.

Lateral device structures using self-aligned fabrication techniques

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of as layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

Surface Damage on GaAs Induced by Reactive Ion Etching and Sputter Etching

Abstract: surface damage induced by reactive ion etching (RIE) using various gases is compared with sputter etching using inert gases. Anisotropic etching of with minimal surface damage can be obtained with most of the RIE conditions used. Sputter etching using inert gases introduces substantial damage on the surface, and the degree of damage is inversely proportional to the ion mass. In addition, we have found that the damage induced by Ar sputter etching can be greatly reduced by the introduction of reactive gases during etching. Recovery of the diode characteristics is observed after removing 500A of the etched surface using wet chemical solution or by removing 200A of the etched surface using RIE in at 30V.

Integrated circuit isolation process

Abstract: A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). The recesses are filled with oxide by growing a field oxide (40) in wide recessed regions (21) using a LOCOS process, while depositing a planarization field oxide (44) in narrow recessed regions (20). After etching the structure to obtain a planar surface, standard procedures are used to fabricate the active devices. The process uses a single photolithographic masking step and results in only a very small loss of the width electrically active regions.

Silicon Cantilever Beams Fabricated by Electrochemically Controlled Etching for Sensor Applications

Abstract: An electrochemically controlled etching of silicon and an integrated circuit technology are used to fabricate 10 μm thick cantilever beams containing integrated devices. Such structures are fabricated by two different methods, each of which is analyzed and the advantages and problems inherent in them stated. The influence of several parameters on the etch rate of silicon and on the quality of the beam surface is examined. Finally, an example of the application of such silicon microstructures to sensors is presented: a vacuum sensor, a novel type of thermal vacuum gauge, based on an integrated silicon thermopile.

Basic mechanisms in laser etching and deposition

Abstract: Laser-induced chemical processing of solid surfaces has the potential for being an important and powerful technique for fabrication of a variety of devices. Successful applications rest on a detailed understanding of the nature of laser-induced reactions and their effects on the properties of materials. In this paper fundamental studies illustrating key features of laser etching and deposition are reviewed. Topics covered include the effect of the choice of precursor and deposition conditions on film composition and morphology, self-propagation of exothermic reactions, thermal and electronic effects in laser-assisted etching of semiconductors, metals and polymers, and special aspects of laser-surface photophysics as they may affect chemical reactions.

Method of making micromachined refractory metal field emitters

Abstract: A method of making a field emitter includes anisotropically etching a single crystal silicon substrate to form at least one funnel-shaped protrusion on the substrate, then conformally depositing a refractory metal onto the funnel-shaped protrusion. Alternatively, single crystal silicon may be anisotropically etched to form at least one funnel-shaped recess in the silicon. The etched surface is doped with an impurity to form an etch-stop layer, the remaining undoped silicon is removed, then the etch-stop layer is conformally deposited with a refractory metal. The funnel-shaped recess can then be back-filled with silicon or another suitable material.

Pulsed CO2 laser etching of polyimide

Abstract: Etching of thin polyimide films in air was investigated using a line tunable, pulsed CO2 laser. The threshold fluence for etching at a wavelength of 944 cm−1 (10.6 μm) exceeds that at 1087 cm−1 (9.2 μm) by a factor of 4. This is consistent with the infrared absorption spectrum which shows polyimide to be significantly more absorbing at 1087 cm−1. As a result, etching at 1087 cm−1 produces a cleaner, more precisely defined region. Analysis of the vapors generated during laser etching shows the simple gases CO2, H2O, and CO to be present.

Manufacture of semiconductor device

Abstract: PURPOSE:To determine correctly the etching completion point in time of a metal layer when the metal layer is adhered on the whole surface of a semiconductor substrate containing a projecting electrode provided on the substrate, and after a bump is fixed on the electrode, the metal layer other than the layer under the electrode is etched to be removed by a method wherein a different monitor membe is provided on the metal layer, and the side etching quantity of the metal layer directly under the member thereof is measured CONSTITUTION:An SiO2 film 2 is adhered on the whole surface of an Si substrate 1 containing a projecting electrode 3 formed on the substrate, and an opening is dug in the film 2 corresponding to the electrode 3 Then a metal layer 5 is adhered extending from the opening thereof over the whole surface of the film 2 to enhance adhesion between a bump 13 to be formed afterward and the already provided electode 3, and to check mutual diffusion, the bump 13 is fixed on the layer 5 positioning on the electrode 3, and a monitor member 14 is formed also on the other region of the layer 5 After then, the exposing part of the layer 5 etched to be removed, while at this time, the side etching quantity of the layer 5 directly under the member 14 is measured, and when the quantity thereof becomes to the prescribed value, it is judged as etching is completed

Semiconductor pressure sensor and method of manufacturing the same

Abstract: A semiconductor pressure sensor composed of a substrate formed adopting a thin-film forming technique and a diaphragm which is formed on the surface of the substrate. The sensor includes an insulating diaphragm film which is formed of an etching-resistant material on the main surface of the semiconductor substrate such as to coat it, at least one etching hole provided such as to penetrate the diaphragm film and reach the substrate, a reference pressure chamber which is formed by etching to remove a part of the semiconductor substrate and a disappearing film through the etching hole, and at least one strain gage which is provided at a predetermined position in the pressure receiving region of the diaphragm film. All the processing steps of the sensor are conducted solely on the main surface of the semiconductor substrate, namely, on a single side. Therefore, it is possible to manufacture the sensor itself utilizing the substantially same technique as the known integrated circuit manufacturing technique and to form the diaphragm with a predetermined thickness such that it may process a thin and precisely dimensioned thickness.

Effect of organic contaminants on the oxidation kinetics of silicon at room temperature

Abstract: The oxidation kinetics of HF‐etched n‐ and p‐doped silicon in air at room temperature have been studied by electron spectroscopy for chemical analysis. No great differences have been found between the n‐ and p‐type oxidation kinetics at the low doping level of the studied samples. The rate of oxide growth on the HF‐etched surface is much lower than that on a silicon surface obtained by fracture in air of a silicon monocrystal. The behavior of a silicon sample fractured in de‐ionized water and then oxidized in air at room temperature is intermediate. The above findings have been interpreted on the basis of surface reactions involving the plasticizers of the HF and water containers. These reactions produce carbon‐rich hydrophobic surfaces which retard the silicon oxide growth. A mechanism for the involved surface reactions is proposed.

Anisotropic silicon etching in fluorinated plasma

Abstract: A method of high rate anisotropic etching of silicon in a high pressure plasma is described. In one embodiment the etching ambient is a mixture of either NF 3 or SF 6 , an inert gas such as nitrogen, and a polymerizing gas such as CHF 3 that creates conditions necessary for anisotropy not normally possible with nonpolymerizing fluorinated gases in a high pressure regime. The etch process is characterized by high etch rates and good uniformity utilizing photoresist or similar materials as a mask. The present process may advantageously be used to etch deep trenches in silicon using a photoresist mask.

Reactive ion stream etching utilizing electron cyclotron resonance plasma

Abstract: Reactive ion stream etching has been developed for highly accurate etching with little bombardment induced damage by utilizing an electron cyclotron resonance (ECR) plasma. The ion energy during etching is controlled by utilizing the interaction between the ECR plasma and a divergent magnetic field, in a low energy range from 20 to 50 eV at low gas pressures of 10−2 Pa. Highly accurate submicron patterns of polysilicon and molybdenum were obtained with high selectivities to SiO2, larger than 30, by using Cl2 gas as the main etching gas.

Dry etching of β‐SiC in CF4 and CF4+O2 mixtures

Abstract: Dry etching of cubic (100)β‐SiC single crystal thin films produced via chemical vapor deposition (CVD) has been performed in CF4 and CF4+O2 mixtures, in both the reactive ion etching (RIE) and plasma etching modes. The latter process yielded measurable etch rates, but produced a dark surface layer which appears, from the results of secondary ion mass spectrometry, to be residual SiC. The RIE samples had no residual layer, but Auger electron spectroscopy did reveal a C‐rich surface. The optimal RIE conditions were obtained with 10 sccm of pure CF4 at 40 mTorr and a power density of 0.548 W/cm2, giving an etch rate of 23.3 nm/min. Neither the increase of temperature between 293 and 573 K, nor the incremental addition of O2 to CF4 to 50%, produced any strong effect on the etch rates of SiC during RIE. Pictorial evidence of fine line structures produced by RIE of β‐SiC films are also presented.

Method of making edge-aligned implants and electrodes therefor

Abstract: METHOD OF MAKING EDGE-ALIGNED IMPLANTS AND ELECTRODES THEREFOR Abstract There is disclosed a process particularly suited for making CCD's. The process comprises the steps of a) depositing a layer of conductive material above a semiconductor substrate; b) forming a patterned mask above the con-ductive layer, the pattern exposing spaced-apart strip portions of the conductive layer; c) ion-implanting dopant strips into the sub-strate through the conductive layer strip portions exposed by the patterned mask; d) removing a portion of the mask but retaining the rest so as to expose the conductive layer over first portions of the substrate that contain an implanted dopant strip and over portions of the substrate adjacent to the first portions; e) forming on the conductive layer between the retained mask portions, strips of a material resistant to an etchant for the conductive material; f) removing the retained mask portions; and g) etching away the conductive layer where the latter is not covered with the etchant-resistant mate-rial so as to leave conductive strips overlying the implanted strips.

Double layer photoresist technique for side-wall profile control in plasma etching processes

Abstract: A photolithographic process useful for VLSI fabrication for achieving side-wall profile control of poly lines, metal lines, contact and via openings. Layers (20, 25) of a first and second photoresist materials are formed on the poly, metal or oxide-covered substrate (10, 15). The top layer (25) is patterned by conventional processes to define the final device geometry. The bottom layer (20) is exposed and overdeveloped to form an overhang structure about the line pattern or the contact/via opening (30). During the subsequent anisotropic plasma-assisted etching step, some ions or particles are passed obliquely over the overhang and bombard the opening corner, the side-wall and the under-cut area. The plasma-assisted etching step not only forms the poly or metal lines, or the contact or via opening (30), but a smoothly tapered side-wall profile. The subsequent metal film (40) deposition step results in a uniform film thickness around the edges of the opening. The process thus alleviates the problem of high contact resistance previously encountered as a result of dry etching the contact or via openings.