Showing papers on "Etching (microfabrication) published in 1987"

Dry etching of silicon carbide

Abstract: The invention comprises a method of etching silicon carbide targets. In one embodiment, a reactive ion plasma is formed from a gas which is easily dissociated into its elemental species in the plasma, for which all of the dissociated elemental species are volatile in the plasma, and for which at least one of the elemental species is reactive with silicon carbide. The silicon carbide target to be etched is positioned on one of the electrodes which is formed from a material with a low sputter yield and which material reacts with a dissociated species to thereby prevent contamination of the target with either sputtered materials from the electrode or polymerized species from the plasma.

Non-uniform gas inlet for dry etching apparatus

Abstract: A gas inlet having a non-uniform array of inlet holes for the non-uniform introduction of an etching gas into a reaction chamber of a dry etching apparatus. The non-uniform introduction of gas compensates for non-uniform characteristics in the dry etching apparatus resulting in a uniform etch.

Pulsed laser etching of high Tc superconducting films

Abstract: Etching of Y‐Ba‐Cu‐O superconducting thin films has been accomplished using a pulsed excimer laser (248 nm, 30 ns). Etch depth as a function of the number of laser pulses was linear over a wide range of incident laser energy densities. An etch threshold energy density of 0.11 J/cm2 was observed and etch rate per pulse scaled linearly with the logarithm of the incident energy density. The dependence is adequately explained by a linear absorption model with an inverse absorption length of 2.3×105 cm−1.

Mechanisms of deposition and etching of thin films of plasma‐polymerized fluorinated monomers in radio frequency discharges fed with C2F6‐H2 and C2F6‐O2 mixtures

Abstract: Deposition and etching of thin plasma‐polymerized fluorinated monomers have been studied in discharges fed with C2F6‐H2 and C2F6‐O2 mixtures, respectively. A parallel plate reactor with thermostated electrodes has been utilized for the present study. The experiments have allowed us to ascertain the role of positive ions and of radicals, as well as the effect of pressure and substrate temperature, on the mechanism of deposition. The mechanism of etching has also been investigated, and it has been found that both O and F atoms contribute to the process through overall first‐order kinetics. Conditions for a selective etching of noncross‐linked films with respect to cross‐linked ones have also been found.

Method of fabricating a LDDFET with self-aligned silicide

Abstract: A method of fabricating a lightly-doped drain field effect transistor (LDDFET) with or without self-aligned silicide (salicide) on a substrate is disclosed. The initial steps include either (1) anisotropic silicon nitride and polysilicon etching steps, an isotropic photoresist erosion step, and a second anisotropic etching of part of the silicon nitride to obtain a ladder-shaped polysilicon gate having a silicon nitride thereon; or (2) an anisotropic polysilicon etch step, an isotropic photoresist erosion step to expose part of the unetched polysilicon, and a second anisotropic polysilicon etch step to remove completely the unmasked polysilicon to obtain the ladder-shaped polysilicon gate. The LDD structure is formed by the implantation of ions to form a heavily-doped source and drain regions and lightly-doped regions under the step of the ladder-shaped polysilicon gate layer. Thereafter, the thin polysilicon step is oxidized completely. After the silicon nitride and silicon dioxide layers are removed, the self-aligned silicide may be applied to form the LDD with salicide.

Method for planarization of a semiconductor device prior to metallization

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

Low‐pressure deposition of high‐quality SiO2 films by pyrolysis of tetraethylorthosilicate

Abstract: The deposition of SiO2 by pyrolysis of tetraethylorthosilicate (TEOS) at pressures below 1 Torr was investigated at temperatures between 650 and 800 °C. We found oxide thickness variations of <±5% for suitable process conditions (PD ≤500 mTorr, wafer spacing ≥4.7 mm, TD <730 °C, deposition rate 16 nm min−1). Tests with 150‐mm wafers showed that uniformities of ±2% can be achieved if the wafer spacing is increased to 10 mm. Raising the deposition pressure improves the step coverage in deep trenches but degrades the thickness uniformity across the wafer. The investigations of etch rates in different media show strong dependences on the anneal temperature for etchants containing HF but only a slight dependence for plasma etching. The dielectric breakdown strength of the oxides was 8 MV cm−1 and the failure rate after 500‐ms current stress at 1 mA cm−2 lower than 20%. We found values for the interface state density of 1×1010 eV−1 cm−2 and for the oxide charge density in the range 3×1010 cm−2 to 2.5×1011 cm−2,...

Field emission vacuum devices

Abstract: A vacuum valve device comprises a substrate on which is formed an updoped silicon layer from which a silicon dioxide layer is grown. First, second and third electrode structures are formed on the silicon dioxide layer by depositing a metallic layer and etching away unwanted portions of the layer. The first electrode structure has a pointed end and/or a sharp edge and/or is formed of low work function material so that, when a suitable voltage is applied between the first and third electrode structures, electrons are emitted from the first electrode structure due to a field emission process. Electrons therefore flow from the first to the third electrode structure substantially parallel to the substrate. The second electrode structure acts as a control electrode.

Synchrotron radiation-excited chemical-vapor deposition and etching

Abstract: Photoexcited chemical‐vapor deposition (CVD) and etching using synchrotron radiation as an exciting light source were experimentally demonstrated. CVD of silicon nitride film and etching of Si and SiO2 by SF6+O2 gases are described in detail. In several reaction systems, it was found that the surface photoexcitation was an important mechanism. Reaction models for gas‐phase excitation and surface excitation were proposed.

A 90-GHz double-drift IMPATT diode made with Si MBE

Abstract: For the first time silicon double-drift IMPATT structures have been grown completely by Si molecular-beam epitaxy. The n-type layers are grown at 750 °C on low-resistivity n+-type substrates followed by p-type layers at 650 °C. The highly doped p+-layers are grown by solid-phase epitaxy in the MBE system. Device design is made for CW operation in W-band. The material is investigated by inspection of beveled samples, defect etching, TEM, SIMS, and spreading resistance measurements. Double-drift flat-profile diodes are housed and mounted employing a technological procedure approved for single-drift diodes. For initial device characterization, dc measurements are performed. Information about doping profile, series, and thermal resistances is obtained. Preliminary RF measurements delivered a maximum output power of 600 mW at 94 GHz with 6.7-percent efficiency from an unoptimized structure.

Synchrotron radiation‐excited chemical‐vapor deposition and etching

Abstract: Photoexcited chemical‐vapor deposition (CVD) and etching using synchrotron radiation as an exciting light source were experimentally demonstrated. CVD of silicon nitride film and etching of Si and SiO2 by SF6+O2 gases are described in detail. In several reaction systems, it was found that the surface photoexcitation was an important mechanism. Reaction models for gas‐phase excitation and surface excitation were proposed.

Manufacture of semiconductor device

Abstract: PURPOSE:To realize a quality MESFET provided with a source, a gate, and a drain with the gaps between them constant and smaller and provided with a gate electrode enhanced in thickness by a method wherein a trench is provided in the surface of a semiconductor layer and, in the trench, a Schottky junction is formed between a gate electrode buried in the trench and the semiconductor layer for the construction of a MESFET. CONSTITUTION:On the semi-insulating GaAs substrate 11, an N-type layer 12 is epitaxially grown. Onto the entire surface of such a wafer, an AuGe layer and then an ohmic metal layer 13 are attached. Heat treatment is accomplished, which is followed by patterning whereby a 2.5mum gap is provided between a source and a drain. The ohmic metal layer 13 and the N-type layer 12 are then subjected to ion beam etching. A plasma SiO2 film 14 is provided and subjected to etching which is accomplished vertical to the substrate surface. Next, three layers of Ti, Pt, and Au are laid on the entire surface, in that order. Ion beam etching is accomplished at 30 deg. to the direction vertical to the substrate surface, after which Au and Pt are retained only at a gate section 15. Etching follows, after which Ti is retained only under the gate section 15 for the completion of a three-layer Schottky gate electrode.

Manufacture of semiconductor device

Abstract: PURPOSE:To obtain a dynamic RAM whose area per cell is reduced and integration density is increased by separating in the longitudinal direction a diffusion layer of opposite conduction type formed on a substrate surface and a diffusion layer of capacitance part to increase the withstand voltage of this part. CONSTITUTION:A first groove 4 is formed on a P-type single crystal silicon substrate 1 by photoetching. That is, the desired regions of Si3N4 film 3, SiO2 film 2 and silicon substrate 1 are subjected to etching in order, and the groove is formed. A SiO2 film 5 is formed on the whole surface of a wafer and reaction ion etching is applied thereon. The first groove 4 is subjected to the deeper etching to form a second groove 44. Boron is doped on the inner wall of the groove 44, and a P diffusion layer 6 is formed, then a capacitance insulating film 8 is formed. After the vapor growth of polycrystalline silicon 9 is applied on the whole surface of a wafer, the polycrystalline on the surface of the Si3N4 film 3 is eliminated and the polycrystalline silicon 9 is buried in the groove 44. After a contact hole 7 is formed by photoetching, an N diffusion layer 10 is formed on the substrate surface of the contact hole part. At this time, the N diffusion layer 10 and the P diffusion layer 6 are separated by about 0.5-1mum so as to obtain a sufficient withstand voltage.

Dry etching apparatus

Abstract: A dry etching apparatus which includes an anode located at an upper side and a cathode located at a lower side which face each other in a vacuum vessel. A high-frequency power can be applied across the anode and the cathode. A flange section extends from the inner wall of the vacuum vessel, and is located between the anode and the cathode. A semiconductor wafer can be placed on the cathode through a tray. The cathode is moved toward the anode together with the tray and the wafer. When the edge portion of the tray abuts against the flange section, the interior of the vacuum vessel is partitioned into an etching chamber and the other chamber. A magnetic field is applied to the etching chamber from outside the vacuum vessel, and an etching gas is also introduced into the etching chamber. When the etching gas is introduced, the interior of the etching chamber is evacuated to be maintained at a predetermined pressure.

Laser-induced chemical etching of silicon in chlorine atmosphere

Abstract: Chemical etching of single-crystalline (100)Si induced by pulsed laser irradiation at 308, 423, and 583 nm has been investigated as a function of the laser fluence and C12 pressure. Without laser-induced surface melting, etching requires Cl radicals which are produced only at laser wavelengths below 500 nm. With low laser fluences (Φ(308 nm) 440 mJ/cm2) etching is thermally activated. In the intermediate region both thermal and non-thermal mechanisms contribute to the etch rate.

An analytical study of etch and etch‐stop reactions for GaAs on AlGaAs in CCl2F2 plasma

Abstract: We have studied selective reactive ion etching of GaAs on AlGaAs in CCl2F2 plasma in situ by optical emission spectroscopy and mass spectrometry and have analyzed etched surfaces, before and after air exposure, by x‐ray photoelectron spectroscopy. Data from etching GaAs samples indicate that volatile arsenic fluorides, chlorides and fluorochlorides, and gallium chlorides are the products formed, leaving a stoichiometric GaAs surface with adsorbed F and Cl for the particular plasma conditions we used. Data from samples etched to AlGaAs, where the etching process stops, demonstrate that the stopping is due to formation of nonvolatile AlF3 and GaClxFy, leaving a surface nearly depleted of arsenic. This etch‐stop ‘‘layer’’ is between 4 and 10 monolayers in thickness. After air exposure this surface consists of gallium and aluminum oxides and a small percentage of arsenic oxide with about the same quantities of Ga, Al, and As as on the surface before exposure to air. This differs from a wet‐etched (in dilute a...

Reactive etching of positive and negative silicon cluster ions by nitrogen dioxide

Abstract: Positively and negatively charged silicon cluster ions, Si+1–8 and Si−1–6, react exothermically with NO2. The predominant reaction is loss of a single silicon atom in the form of SiO. This reaction repeats sequentially such that the clusters are ‘‘etched’’ down to monatomic silicon ions. Charge transfer to form NO−2 also occurs for Si−1–4. Previous results have shown that all Si−1–6 exhibit electron transfer to WF6. Together, these observations bracket the electron affinities of the neutral silicon clusters: EA (Si2–4)≤2.6 eV and 2.6 eV≤EA (Si5–6)≤3.7 eV. The reaction rates for the silicon cluster cations decrease slowly from 7.3±0.8×10−10 to 0.4±0.2×10−10 cm3 molecule−1 s−1 with increasing cluster size for Si+1–8. Silicon cluster anion reaction rates show a slight decrease from 15±1×10−10 to 5.0±0.1×10−10 cm3 molecule−1 s−1 with increasing cluster size for Si−1–6. The ionic silicon cluster reactivity is explained by a radical–radical coupling mechanism involving the unpaired electron on NO2 and an unpair...

Method for etching contact vias in a semiconductor device

Abstract: A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

Influence of doping on the etching of Si(111).

Abstract: Exposure of solid surfaces to reactive gases (or radicals) often leads to chemical reactions which produce volatile products. These are frequently called etching reactions. The example discussed in this paper involves the reaction of XeF/sub 2/ with Si(111) to produce SiF/sub 4/(gas). It will be shown that the etch rate depends strongly upon the concentration and type of dopant. It also depends upon the thickness of the fluorosilyl (SiF/sub x/) layer on the surface. The trends previously observed in plasma-assisted etching environments are shown to also occur in the XeF/sub 2/-Si reaction. A simple model will be developed which indicates a strong correlation between the number of negative ions on the surface and the etch rate. The model is based upon some of the ideas originally proposed by Mott and Cabrera to describe oxide growth and on the Poisson-Boltzmann equation which describes the space charge at a semiconductor interface.

Method of metallizing ceramic material

Abstract: A method of metallizing a ceramic material by forming a metal thin film through electroless plating, chemically etching the metal thin film after heat treatment and metallizing the surface of the ceramic material through electroless plating after the etching.

Relation of polymer structure to plasma etching behavior: Role of atomic fluorine

Abstract: Plasma etching of organic polymers typically involves the use of feed gas mixtures of oxygen with a fluorocarbon. The reactive etchants are generally accepted to be atomic fluorine and atomic oxygen. The roles of these etchants are discussed with special attention being given to the part played by atomic fluorine. Mechanisms are inferred theoretically from a molecular orbital study, and experimentally from the surface composition of plasma treated samples. Hydrogen abstraction by fluorine leads to enhanced etching of saturated polymer structures while addition of fluorine is the dominant mechanism for unsaturated moieties. Etch rate behavior for polyimide, polyisoprene, and polyethylene as a function of gas composition is discussed in terms of the affinity that fluorine has for the surface of the saturated and unsaturated polymers.

Etching in a pulsed plasma

Abstract: The etching of silicon in a pulsed plasma using SF6 gas is investigated. For short pulses the Si etch rate for a pulsed plasma is essentially the same as for the continuous plasma, in spite of the duty cycle being only 20%. An heuristic model of the etching has been developed which accurately predicts the pulsed plasma etch rates and sets limits on important parameters, such as the number of F atoms yielded by the SF6, the reaction probability of F with Si, and the overall efficiency of the etching process.

Manufacture of semiconductor device

Abstract: PURPOSE: To realize accurate conformity and minimum parasitic capacitance, by exposing photoresist to a light by using an opaque pattern formed on a substrate as a mask, via a transparent substrate. CONSTITUTION: A gate electrode G1 composed of chromium is formed on a transparent glass substrate 2, and covered with an insulating layer 4, an indium/ tin oxide layer 5 and a photoresist layer 7, which is irradiated with UV rays through the substrate 2 in such a manner that the photoresist is eliminated on the opaque region of the gate electrode G1 in the case of development. Thereby the exposed conductive region is etched. In order to define a contact region, the substrate is covered with photoresist and etched by exposure from the front surface of the substrate via a mask M2. A cadmium selenide layer 9 and a photoresist layer 10 are deposited on the insulating layer 4 and a defined contact 5, exposed to UV rays and developed. By etching the cadmium selenide layer, a channel region C is formed. Thereby overlap of electrodes is not generated and parasitic capacitance can be reduced.

Rie process for etching silicon isolation trenches and polycides with vertical surfaces

Abstract: Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a fluorochlorohydrocarbon (e.g., CCl₂F₂, CHCl₂F₂, CCl₄ or CCl₃F), SF₆, O₂ and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the fluorochlorocarbon to SF₆ and the following composition: 1-4 % of SF₆, 3-10 % of O₂, 74-93 % of He and 3-10 % of fluorochlorohydrocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.

Novel process for integration of optoelectronic devices using reactive ion etching without chlorinated gas

Abstract: A new process for RIE of III?V compound semiconductors using mixtures of CH4, Ar and H2 as the etching gas is presented This process can be successfully applied to most III-V materials used in micro-optoelectronic technology

Silicon etch rate enhancement

Abstract: This invention is directed to a method for increasing the etch rate of a single crystal silicon wafer in an anisotropic etching solution. This method comprises applying a mask material to a portion of one face of the wafer and a metal coating to substantially the entire surface of an opposite face of the wafer which renders the electrode potential of the masked, metal coated single crystal silicon wafer more anodic than that of a masked, single crystal silicon wafer alone, and exposing the coated wafer to a suitable anisotropic etching solution. This method may further comprise applying an external anodic voltage to the masked, metal coated single crystal silicon wafer, which voltage is less than that which causes the electrode potential of the masked, metal coated single crystal silicon wafer to exceed the passivation potential of the masked, single crystal silicon wafer.