Showing papers on "Etching (microfabrication) published in 1991"

Thin film deposition and microelectronic and optoelectronic device fabrication and characterization in monocrystalline alpha and beta silicon carbide

Abstract: The deposition of silicon carbide thin films and the associated technologies of impurity incorporation, etching, surface chemistry, and electrical contacts for fabrication of solid-state devices capable of operation at temperatures to 925 K are addressed. The results of several research programs in the United States, Japan and the Soviet Union, and the remaining challenges related to the development of silicon carbide for microelectronics are presented and discussed. It is concluded that the combination of alpha -SiC on alpha -SiC appears especially viable for device fabrication. In addition, considerable progress in the understanding of the surface science, ohmic and Schottky contacts, and dry etching have recently been made. The combination of these advances has allowed continual improvement in Schottky diode p-n junction, MESFET, MOSFET, HBT, and LED devices. >

Micromachined silicon sensors for scanning force microscopy

Abstract: We have developed a batch process for the microfabrication of silicon force sensors. A force sensor typically consists of a tip mounted onto a cantilever which is connected to a handling piece. The sensors are being used as microprobes and force transducers in scanning force microscopes. Our sensors are etched from single crystal silicon. The process, which mainly involves a combination of wet and dry etching techniques, results in cantilevers and tips suitable as general purpose force sensors. The newly developed batch microfabrication process is superior to the process which uses wet etching of individual metal wires and it differs substantially from the known process to produce thin film cantilevers with and without integrated tips. The sensors have been applied in various microscopes, and with different types of operation including the repulsive, attractive, and magnetic force mode.

Chemical etching of vicinal Si(111): Dependence of the surface structure and the hydrogen termination on the pH of the etching solutions

Abstract: Infrared spectroscopy is used to study the etching process of stepped Si(111)9° surfaces as a function of the pH of the etching HF solutions. This process results in complete H termination of the silicon surface, including terraces, steps, and defects; the surface structure can therefore be well studied using infrared (IR) spectroscopy. Polarized IR absorption spectra of the Si–H stretching vibrations (i.e., in the region 2060–2150 cm−1) vary dramatically as the pH of the etching solutions increases from 2.0 to 7.8. In general, higher pH solutions yield sharper bands and more easily assigned spectra, making it possible to identify the step and terrace species and thus to infer the surface structure and step morphology (i.e., to investigate the etching process). The data are explained by a model involving different etching rates for each individual surface species: The highest rate of removal is for isolated adatom defects located on (111) planes and the lowest is for the ideally H‐terminated (111) planes ...

Charging of pattern features during plasma etching

Abstract: The localized charging of a rectangular trench during the plasma etching of a perfectly insulating surface was modeled assuming an isotropic electron flux and monodirectional ion bombardment. The field set up by the localized charging acts to deflect arriving ions, modifying the ion flux densities within the feature, and thus, etching rates. Preliminary simulations indicate that this may be important in the shaping of etching profiles.

Semiconductor device having an interlayer insulating film of high crack resistance

Abstract: A method of manufacturing a semiconductor device having a flat surface and an interlayer insulating film having superior crack resistance is disclosed. A first silicon oxide film having a superior crack resistance is formed on a semiconductor substrate so as to cover the surface of a stepped pattern. A second silicon oxide film having a superior step coverage is deposited on the above-mentioned first silicon oxide film so as to fill the recessed portions of said stepped pattern and to cover said stepped pattern. The above-described second silicon oxide film is etched to a prescribed thickness. A third silicon oxide film superior in filling of recesses is placed into the recessed portions existing on the surface of the above-described second silicon oxide film after its etching. A fourth silicon oxide film is formed on said semiconductor substrate including the above-described second silicon oxide film and third silicon oxide film.

Semiconductor member and process for preparing semiconductor member

Abstract: A process for preparing a semiconductor member by forming a member having a non-porous monocrystalline semiconductor region on a porous monocrystalline semiconductor region, bonding the insulating surface of a member to the surface of the non-porous monocrystalline semiconductor region, and then removing the porous monocrystalline semiconductor region by etching.

Method and apparatus for spatially uniform electropolishing and electrolytic etching

Abstract: In an electropolishing or electrolytic etching apparatus the anode is separated from the cathode to prevent bubble transport to the anode and to produce a uniform current distribution at the anode by means of a solid nonconducting anode-cathode barrier. The anode extends into the top of the barrier and the cathode is outside the barrier. A virtual cathode hole formed in the bottom of the barrier below the level of the cathode permits current flow while preventing bubble transport. The anode is rotatable and oriented horizontally facing down. An extended anode is formed by mounting the workpiece in a holder which extends the electropolishing or etching area beyond the edge of the workpiece to reduce edge effects at the workpiece. A reference electrode controls cell voltage. Endpoint detection and current shut-off stop polishing. Spatially uniform polishing or etching can be rapidly performed.

Surface micromachined pressure transducers

Abstract: Typical IC processing is fundamentally two dimensional; sensors are three-dimensional structures. In surface micromachining, two-dimensional IC processing is extended to sensor structures by the addition of one or more sacrificial layers which are removed by lateral etching. The resulting sensor structures involve the substrate and one or more deposited films which form the intended micromechanical component. The concepts of this type of sensor manufacturing are readily demonstrated by considering absolute pressure transducers in some detail. Absolute pressure transducers involve a vacuum-sealed cavity and a deformation sensing technique. The cavity is formed from the substrate and a low-pressure chemical vapor deposited polycrystalline silicon film. The mechanical properties of this film must be controlled well enough to allow the device to be designed. This implies morphological control during processing. Optimized films which do exhibit controlled compressive or tensile strains exclude oxygen or nitrogen and are therefore not modified by extended hydrofluoric acid etches. Their mechanical behavior is monitored by micromechanical test structures which measure Euler buckling and thereby determine the value of the built-in strain. The cavity vacuum is established by reactive sealing. Long-term vacuum integrity is achieved by a low-stress silicon nitride barrier which also acts as a dielectric isolation barrier. Sensing is accomplished via deposited polysilicon resistors. These devices behave like metal resistors in terms of their temperature coefficient of resistance and noise figure. Their piezoresistive behavior is larger than that of typical metal film structures and smaller than that of single-crystal resistors. Pressure sensors with four diaphragms, two active and two inactive, have been constructed and optimized towards manufacturability. The measured performance is excellent and agrees with the predictions of the design algorithm.

Semiconductor transducer or actuator utilizing corrugated supports

Abstract: A semiconductor transducer or actuator is disclosed. The transducer and actuator each include a deflecting member with corrugations producing increased vertical travel which is a linear function of applied force. An accurate and easily controlled method that is insensitive to front-to-back alignment is also disclosed for forming uniform corrugations of precise thickness; independent of the thickness of the deflecting member. The cross-sectional shape of the corrugations is not limited by the etching technique, so that any configuration thereof is enabled.

Etching roughness for (100) silicon surfaces in aqueous KOH

Abstract: The quality of vertical roughness produced by the etching of Si in aqueous KOH has been studied by varying several experimental parameters such as molarity, time of etching, temperature, and stirring. We note that at room temperature, unstirred etching is smoother at low and high molarities, and etch rate and roughness both peak near 5–6 M. With no stirring, roughness increases as a function of etch time, then levels off. With stirring, roughness decreases, especially around the peak etch rate near 5–6 M. For a fixed molarity like 5 M, unstirred etching becomes smoother with increasing temperature even as the etch rate increases rapidly. Such results suggest that masking by hydrogen bubbles or silicate etch products is the principle origin of vertical roughness. Bubble properties as a function of molarity and stirring (as determined from electrolysis experiments) are used to suggest a pseudo‐masking model to explain some roughness properties.

Homogeneous hydrogen-terminated Si(111) surface formed using aqueous HF solution and water

Abstract: Aqueous HF etching of silicon surface removes surface oxide, leaving a silicon surface terminated by atomic hydrogen. We studied the effect of the immersion in water, following HF etching, on the surface hydride structure and flatness, by measuring Si‐H stretching vibration using infrared absorption spectroscopy. Immersion at 20 °C flattens the Si(111) surface, which is atomically rough just after etching, to some extent. Boiling water (100 °C) produces an atomically flat surface homogeneously covered with silicon monohydride (—SiH) normal to the surface and free of oxidation. The surface has a low defect density of less than 0.5%.

Silicon diaphragm piezoresistive pressure sensor and fabrication method of the same

Abstract: A silicon diaphragm piezoresistive pressure sensor having a diaphragm formed by a single-sided fabrication method. The pressure sensor is made up of a substrate on which there is a diaphragm at or near the surface of the substrate with a chamber under the diaphragm. The pressure sensor is fabricated by undercutting a silicon substrate to form a diaphragm and a cavity within the bulk of the substrate under the diaphragm. The fabricating steps including a) forming a buried low resistive layer under a predetermined diaphragm region; b) converting the low resistance layer into porous silicon by anodization of silicon in a concentrated hydrofluoric acid solution; c) removing the porous silicon by selective etching; d) filling the openings formed in the etching of porous silicon with a deposited material to form a sealed reference chamber. Adding appropriate means to the exterior of the diaphragm and substrate to detect changes in pressure between the reference chamber and the surface of the substrate.

Oxidation sharpening of silicon tips

Abstract: Sharp microtips of silicon have potential applications as field emitters and as electrical or mechanical microsensors. This study describes a single unified etching/oxidation treatment that results in uniform tips with controlled radii of atomic dimensions or larger. Variations in the etching/oxidation treatment form multiple tips with two or four tips per etched pyramid, which offer the possibility of higher emission current density for field emitter applications, and higher sensitivity for microsensor applications.

Self-aligning contact and interconnect structure

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Low‐temperature dry etching

Abstract: Low‐temperature electron‐cyclotron‐resonance microwave plasma etching and reactive ion etching are described for ULSI device fabrication. Highly selective anisotropic etching at a high rate, which implies dry etching without tradeoffs, is performed without changing the discharge parameters. This etching is only achieved at reduced wafer temperatures. The etching mechanism and the model are discussed based on the etching yield results obtained by the mass‐selected reactive ion beam etching experiments. The new etching system and the etching properties obtained for the low‐temperature etching are reviewed comparing those obtained in the conventional reactive ion etching and electron‐cyclotron‐resonance microwave plasma etching.

Experimental optimization of an anisotropic etching process for random texturization of silicon solar cells

Abstract: A multifactor experimental investigation of silicon surface texturing was conducted using aqueous potassium-hydroxide (KOH) solutions with isopropyl alcohol (IPA) added as a complexing agent. Czochralski, magnetic-Czochralski, and float-zone silicon wafers of different resistivities with both polished and lapped surfaces were included in the experiment. Process variables considered were solution temperature, time in solution, degree of mechanical mixing, KOH concentration, and IPA concentration. Using hemispherical reflectance as the primary gauge of success, process variables that resulted in an effective surface texture with reflectance less than 12% prior to antireflection coating were identified. Of particular interest was a low-temperature (70 degrees C) process with less than 2% concentration of both KOH and IPA and wide process variable tolerances. >

Thin oxide charging current during plasma etching of aluminum

Abstract: CV measurement is shown to be a more sensitive technique for characterizing plasma-etching induced damage than oxide breakdown. Plasma etching of Al is shown to produce severe distortions in the oxide CV characteristics, from which one can easily deduce the plasma charging current over many orders of magnitude. A clear radial variation of stressing is found and the charging current increases in proportion to the Al peripheral length rather than the area. Using the measured 10-pA/ mu m of the charging current, one should be able to predict the impact of this etch process on oxide integrity and interface stability for a given antenna geometry. >

Infrared thermographic method and apparatus for etch process monitoring and control

Abstract: An infrared television camera (20) monitors the etching of a substrate (26) in-situ in an etch chamber (24). Temporal and spatial resolution of IR emissions is obtained by monitoring the top surface of the substrate (26) in two-dimensions throughout the course of the etching process. Anomalies in temperature detected on the top surface of the substrate (26) can indicate defects in the substrate (26) itself or in the operation of the etching apparatus. Process feedback control is achieved by adjusting various parameters of the etching apparatus (i.e., gas-pressure, flow pattern, magnetic field, coolant flow to electrode, or the like) to compensate for etching anomalies. Etch uniformity and etch endpoint monitoring is achieved by monitoring the IR emissions resulting from exothermic reaction of the film being etched. IR emissions decline at the end of an exothermic etch reaction. Particulate matter which might otherwise harm the substrate (26) can be identified in the gas-phase with a second IR television camera (34) which images the region above the substrate (26). Particulate matter appears as localized "hot spots" within the gas plasma, and the identification of particulate matter allows corrective measures to be taken.

Plasma generating device and method of plasma processing

Abstract: A plasma generating device and a method for etching a minute region of a substrate under atmospheric pressure are disclosed. A gas containing helium as the main ingredient is glow discharged under atmospheric pressure, a halide is added to the discharge so as to activate the halogen element, and a solid material (substrate) such as silicon is chemically etched by using the radicals. At that time, a magnetic field acts on the discharge so as to draw out electrons and ions to the surface of the substrate, thereby increasing the radical density in the vicinity of the surface of the substrate and the etching rate.

Resonant beam pressure sensor fabricated with silicon fusion bonding

Abstract: A resonant pressure sensor has been fabricated which consists of a single-crystal silicon beam located in the center of a single-crystal silicon diaphragm. The beam is excited electrostatically and its motion are detected by piezoresistors. The structure is fabricated with silicon fusion bonding. Overall measurement accuracies of 0.01% have been achieved. This sensor has been designed to meet the exacting standards required for aerospace air data computers and engine control applications where achievable accuracies of 0.1% absolute pressure are required. The principle of operation is imply to measure the change in resonant frequency of a micromachined silicon beam as the pressure exerted on the sensor's diaphragm is changed. >

Manufacture of semiconductor device

Abstract: PURPOSE:To suppress the deterioration of a gate oxide film by a method wherein a gate is formed on a substrate and thereafter, silicon is implanted in drain regions for N layer formation and a polysilicon region and after this, an impurity for drain formation is implanted and the impurities are electrically activated in such a way as to perform a heat treatment. CONSTITUTION:Boron is channel-doped to a silicon substrate 1 and thereafter, a gate oxide film 2 is formed. Then, a polysilicon film 3 is deposited and the films 2 and 3 located at regions other than a gate are removed by etching. After this, a resist 5 is deposited on regions other than regions, where are used as drain regions 6 for N layer formation, and the gate region and silicon is implanted in the regions 6 for N layer formation and the polysilicon region using this resist 5 as a mask. Then, the resist 5 is removed, an oxide film 4 is formed on the gate and arsenic is ion- implanted using this film 4 as a mask to form N layer. After this, after an oxide film is deposited, sidewalls 9 are formed by anisotropic etching and arsenic is implanted to form N layers 8. After this, each impurity enters the position of the lattice of a silicon crystal by a heat treatment and is electrically activated. Thereby, gentle concentration distributions can be respectively obtained from a channel region toward the drain layers.

Principles of wet chemical processing in ULSI microfabrication

Abstract: Fine patterning technology for integrated device manufacturing requires properties such as surface cleanliness, surface smoothness, complete uniformity, and complete etching linearity in wet chemical processing. An improved chemical composition for buffered hydrogen fluoride (BHF:NH/sub 4/F+HF+H/sub 2/O) is determined based on fundamental research into the chemical reaction mechanism of BHF and SiO/sub 2/. Advanced wet chemical processing based on investigation of chemical reaction mechanisms and properties of liquid chemicals, concentrating on the SiO/sub 2/ patterning process by BHF, is described. The principles of wet chemical processing in silicon technology are based on the following: the determination of the dominant reaction (etching) species, the influence of the solubility of the etching products in BHF on etching uniformity and linearity, stability of chemical composition without solid-phase segregation, and an improvement of the wettability of liquid chemicals on the wafer surface by the addition of a surfactant. >

Method of etching vias without sputtering of underlying electrically conductive layer

Abstract: A process for etching of silicon oxide/nitride such as silicon dioxide, silicon nitride or oxynitride. The process includes etching a silicon oxide/nitride layer to expose an underlying electrically conductive layer and provide a via extending through the silicon oxide/nitride layer to the electrically conductive layer. The etching is performed by exposing the silicon oxide/nitride layer to an etching gas in an ionized state in a reaction chamber of a plasma generating device. The etching gas includes a fluoride-containing gas and a passivating gas which is present in an amount effective to suppress sputtering of the electrically conductive layer when it is exposed to the etching gas during the etching step. The passivating gas can be nitrogen gas and the fluoride-containing gas can be CF 4 , CHF 3 , C 2 F 6 , CH 2 F 2 , SF 6 , other Freons and mixtures thereof. The etching gas can also include a carrier gas such as Ar, He, Ne, Kr or mixtures thereof. The etching can be reactive ion etching or plasma etching and the etching gas can be exposed to a microwave electric field and/or a magnetic field during the etching step. The etching gas can achieve 350% overetching while preventing sputtering of the electrically conductive layer which can be Al, Al alloys, Ti, TiN, TiW and Mo.

Method for roughening a silicon or polysilicon surface for a semiconductor substrate

Abstract: This invention relates to a method for roughening a silicon or polysilicon substrate of a semiconductor. The method includes the steps of: depositing a metal layer onto the substrate, heating the metal layer and substrate through to form a metal silicide on the substrate by reaction of the metal layer and substrate, and removing the metal silicide and a metal oxide by selective etching to expose the roughened surface. The actual etching process may be a two-step procedure. A first etch uses ammonium hydroxide and hydrogen peroxide to remove the oxide layer formed with the silicide. A second etch uses hydrofluoric acid to remove the silicide.

Plasma–surface interactions in fluorocarbon etching of silicon dioxide

Abstract: The major species present in a fluorocarbon plasma environment were simulated and independently controlled using radical and ion beams in an ultrahigh‐vacuum apparatus. The beams used in this study were chosen to determine the importance of CFx radicals in a CF4 plasma; the beams included F and CF2, with a beam of Ar+ to simulate energetic ion bombardment. Both CF2 and F enhance the etching yield of SiO2 under energetic Ar+ bombardment; however, the enhancement with F is twice that seen with CF2 at similar fluxes. When CF2 and F fluxes are used simultaneously, F dominates and the CF2 flux has little effect on the overall etching yield. Combined with previous work on Si substrates, these results are consistent with qualitative theories for SiO2/Si selectivity in fluorocarbon plasmas. Possible elementary steps in the ion‐enhanced etching process are proposed and reduced to a two‐parameter model which represents the process as ion‐enhanced neutral adsorption followed by ion‐induced reaction to form volatile ...

Method of etching SiO2 dielectric layers using chemical mechanical polishing techniques

Abstract: A method of planarizing SiO 2 containing dielectric in semiconductor wafer processing comprising: a) providing a layer of undoped SiO 2 atop a wafer; b) depositing a layer of borophosphosilicate glass atop the layer of undoped SiO 2 ; and c) chemical mechanical polishing the borophosphosilicate glass layer selectively relative to the underlying layer of undoped SiO 2 layer and using the layer of undoped SiO 2 as an effective chemical mechanical polishing end-point etch stop to prevent further etching of the borophosphosilicate glass and produce a substantially planar upper wafer surface of dielectric.

Semiconductor processor apparatus with dynamic wafer vapor treatment and particle volatilization

Abstract: Disclosed are apparatuses and methods for improved processing of semiconductor wafers (20) and the like using vapor phase processing chemicals, particularly aqueous hydrofluoric acid etchants. Homogeneous vapor mixtures are generated from homogeneous liquid mixtures. Means for recirculating, mixing and agitating the liquid phase reactants (40) are provided. In some embodiments the liquid phase is advantageously circulated through a chemical trench within the processing bowl (14). Exposure of wafers to vapors from the chemical trench can be controlled by a vapor control valve which is advantageously the bottom of the processing chamber. The wafer is rotated or otherwise moved within the processing chamber to provide uniform dispersion of the homogeneous reactant vapors across the wafer surface and to facilitate vapor circulation to the processed surface. A radiative volatilization processor can be utilized to volatilize reaction by-products which form under some conditions. The apparatuses provide efficient uniform etching with low particle count performance.

Plural level chip masking

Abstract: A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. Both the wafer and the mask are fabricated by a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist and other ones of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure.