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Showing papers on "Etching (microfabrication) published in 1998"


Journal ArticleDOI
01 Aug 1998
TL;DR: In this article, the available etching methods fall into three categories in terms of the state of the etchant: wet, vapor, and plasma, and they are reviewed and compared by comparing the results, cost, complexity, process compatibility, and other factors.
Abstract: Bulk silicon etching techniques, used to selectively remove silicon from substrates, have been broadly applied in the fabrication of micromachined sensors, actuators, and structures. Despite the more recent emergence of higher resolution, surface-micromachining approaches, the majority of currently shipping silicon sensors are made using bulk etching. Particularly in light of newly introduced dry etching methods compatible with complementary metal-oxide-semiconductors, it is unlikely that bulk micromachining will decrease in popularity in the near future. The available etching methods fall into three categories in terms of the state of the etchant: wet, vapor, and plasma. For each category, the available processes are reviewed and compared in terms of etch results, cost, complexity, process compatibility, and a number of other factors. In addition, several example micromachined structures are presented.

780 citations


Journal ArticleDOI
TL;DR: In this paper, the structure and porosity of porous silicon matrixes were characterized by scanning force microscopy and scanning electron microscopy (SEM), Brunnauer−Emmett−Teller nitrogen adsorption isotherms, and reflectance interference spectroscopy.
Abstract: We present in this paper that porous silicon can be used as a large surface area matrix as well as the transducer of biomolecular interactions. We report the fabrication of heavily doped p-type porous silicon with pore diameters that can be tuned, depending on the etching condition, from approximately 5 to 1200 nm. The structure and porosity of the matrixes were characterized by scanning force microscopy (SFM) and scanning electron microscopy (SEM), Brunnauer−Emmett−Teller nitrogen adsorption isotherms, and reflectance interference spectroscopy. The thin porous silicon layers are transparent to the visible region of the reflectance spectra due to their high porosity (80−90%) and are smooth enough to produce Fabry−Perot fringe patterns upon white light illumination. Porous silicon matrixes were modified by ozone oxidation, functionalized in the presence of (2-pyridyldithiopropionamidobutyl)dimethylmethoxysilane, reduced to unmask the sulfhydryl functionalities, and coupled to biotin through a disulfide-bon...

382 citations


Journal ArticleDOI
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

358 citations


Patent
Yan Ye1, Pavel Ionov1, Allen Zhao1, Peter Hsieh1, Diana Xiaobing Ma1, Chun Yan1, Jie Yuan1 
19 Oct 1998
TL;DR: In this paper, a multi-layered masking structure is used, which includes a layer of high-temperature organic-based masking material overlaid by either a patterned layer of inorganic masking materials or by a surface imageable organic masking mixture.
Abstract: A first embodiment of the present invention pertains to a method of patterning a semiconductor device conductive feature while permitting easy removal of any residual masking layer which remains after completion of the etching process. A multi-layered masking structure is used which includes a layer of high-temperature organic-based masking material overlaid by either a patterned layer of inorganic masking material or by a layer of patterned high-temperature imageable organic masking material. The inorganic masking material is used to transfer a pattern to the high-temperature organic-based masking material and is then removed. The high-temperature organic-based masking material is used to transfer the pattern and then may be removed if desired. This method is also useful in the pattern etching of aluminum, even though aluminum can be etched at lower temperatures. A second embodiment of the present invention pertains to a specialized etch chemistry useful in the patterning of organic polymeric layers such as low k dielectrics, or other organic polymeric interfacial layers. This etch chemistry is useful for mask opening during the etch of a conductive layer or is useful in etching damascene structures where a metal fill layer is applied over the surface of a patterned organic-based dielectric layer. The etch chemistry provides for the use of etchant plasma species which minimize oxygen, fluorine, chlorine, and bromine content.

325 citations


Journal ArticleDOI
TL;DR: In this article, the orientation dependence in chemical anisotropic etching of single-crystal silicon was evaluated for a wide range of etching conditions, including KOH concentrations of 30 to 50% and temperatures of 40 to 90 °C.
Abstract: We have evaluated the orientation dependence in chemical anisotropic etching of single-crystal silicon. Etch rates for a number of crystallographic orientations have been measured for a wide range of etching conditions, including KOH concentrations of 30 to 50% and temperatures of 40 to 90 °C. Though the etchants all consist of the same components KOH and water, the orientation dependence varies considerably with change in etchant temperature and concentration. The resulting etch-rate database allows numerical prediction of etch profiles of silicon, necessary for the process design of microstructures. Changing the KOH concentration yields different etch profiles both analytically and experimentally.

304 citations


Journal ArticleDOI
TL;DR: In this paper, a plasma jet was developed for etching materials at atmospheric pressure and between 100 and C. Gas mixtures containing helium, oxygen and carbon tetrafluoride were passed between an outer, grounded electrode and a centre electrode, which was driven by 13.56 MHz radio frequency power at 50 to 500 W. At a flow rate of, a stable, arc-free discharge was produced.
Abstract: A plasma jet has been developed for etching materials at atmospheric pressure and between 100 and C. Gas mixtures containing helium, oxygen and carbon tetrafluoride were passed between an outer, grounded electrode and a centre electrode, which was driven by 13.56 MHz radio frequency power at 50 to 500 W. At a flow rate of , a stable, arc-free discharge was produced. This discharge extended out through a nozzle at the end of the electrodes, forming a plasma jet. Materials placed 0.5 cm downstream from the nozzle were etched at the following maximum rates: for Kapton ( and He only), for silicon dioxide, for tantalum and for tungsten. Optical emission spectroscopy was used to identify the electronically excited species inside the plasma and outside in the jet effluent.

291 citations


Journal ArticleDOI
TL;DR: In this paper, a photoelectrochemical etching process was used to reveal the dislocation microstructure of n-type GaN films by selectively removing material between dislocations.
Abstract: Gallium nitride is used to fabricate high brightness blue and green light-emitting diodes in spite of high densities of extended structural defects. We describe a photoelectrochemical etching process that reveals the dislocation microstructure of n-type GaN films by selectively removing material between dislocations. The GaN whiskers formed by the etching have diameters between 10 and 50 nm and lengths of up to 1 μm. A correlation between the etched features and threading dislocations in the unetched film is confirmed through transmission electron microscopy studies. The whisker formation is believed to be indicative of electrical activity at dislocations in GaN.

235 citations


Patent
15 Oct 1998
TL;DR: In this paper, a process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, nonhomogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etch chamber 30 is presented.
Abstract: A process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, non-homogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etching chamber 30. In the etching step, process gas comprising etchant gas is used to etch a substrate 25 in the etching chamber 30 thereby depositing etch residue inside the chamber 30. Cleaning gas is added to the process gas for a sufficient time and in a volumetric flow ratio that is sufficiently high, to react with and remove substantially all the etch residue deposited by the process gas. The present method advantageously cleans the etch residue in the chamber 30, during the etching process, and without use of separate cleaning, conditioning, and seasoning process steps.

223 citations


Journal ArticleDOI
TL;DR: In this paper, a model is developed that describes the etch kinetics through a fluorocarbon layer based on a fluorine diffusion transport mechanism, which is consistent with the data when one or two of the fol...
Abstract: For various fluorocarbon processing chemistries in an inductively coupled plasma reactor, we have observed relatively thick (2–7 nm) fluorocarbon layers that exist on the surface during steady state etching of silicon. In steady state, the etch rate and the surface modifications of silicon do not change as a function of time. The surface modifications were characterized by in situ ellipsometry and x-ray photoelectron spectroscopy. The contribution of direct ion impact on the silicon substrate to the etching mechanism is reduced with increasing fluorocarbon layer thickness. Therefore, we consider that the silicon etch rate is controlled by a neutral etchant flux through the layer. Our experimental data show, however, that ions play an import role in the transport of silicon etching precursors through the layer. A model is developed that describes the etch kinetics through a fluorocarbon layer based on a fluorine diffusion transport mechanism. The model is consistent with the data when one or two of the fol...

223 citations


Journal ArticleDOI
TL;DR: In this paper, the authors demonstrate well-controlled crystallographic etching of wurtzite GaN grown on c-plane sapphire using H3PO4, molten KOH, KOH dissolved in ethylene glycol, and NaOH, with etch rates as high as 3.2 μm/min.
Abstract: We demonstrate well-controlled crystallographic etching of wurtzite GaN grown on c-plane sapphire using H3PO4, molten KOH, KOH dissolved in ethylene glycol, and NaOH dissolved in ethylene glycol between 90 and 180 °C, with etch rates as high as 3.2 μm/min. The crystallographic GaN etch planes are {0001}, {1010}, {101 1}, {101 2}, and {1013}. The vertical {1010} planes appear perfectly smooth when viewed with a field-effect scanning electron microscope. The activation energy is 21 kcal/mol, indicative of reaction-rate limited etching.

214 citations


Journal ArticleDOI
TL;DR: In this paper, a model based on the symmetry of the SiC unit cell and crystal miscut was proposed for 6H and 4H-SiC(0001) surfaces.
Abstract: Hydrogen etching of 6H- and 4H-SiC(0001) surfaces is studied. The aspolished substrates contain a large number of scratches arising from the polishing process which are eliminated by hydrogen etching. Etching is carried out in a flow of hydrogen gas at atmospheric pressure and temperatures around 1600-1700 C attained on a tantalum strip heater. Post-etching atomic force microscopy (AFM) images show periodic arrays of atomically flat terraces that are a few thousand A wide. These terraces are separated by steps 15 A high in the directions. Often, the surface is seen to be faceted with steps on neighbouring facets forming 60 angles and offset in the c-direction by half a unit cell. Images of incompletely etched surfaces show early stages of etching where one can see remnants of surface damage in the form of arrays of hexagonal pits. On the larger scale, the surface has a hill-and-valley type morphology. The observed features are interpreted in a model based on the symmetry of the SiC unit cell and crystal miscut.

Patent
01 Oct 1998
TL;DR: In this paper, an elastomeric stamp is deformed during and/or prior to using the stamp to print a self-assembled molecular monolayer on a surface.
Abstract: Improved methods of forming a patterned self-assembled monolayer on a surface and derivative articles are provided. According to one method, an elastomeric stamp is deformed during and/or prior to using the stamp to print a self-assembled molecular monolayer on a surface. According to another method, during monolayer printing the surface is contacted with a liquid that is immiscible with the molecular monolayer-forming species to effect controlled reactive spreading of the monolayer on the surface. Methods of printing self-assembled molecular monolayers on nonplanar surfaces and derivative articles are provided, as are methods of etching surfaces patterned with self-assembled monolayers, including methods of etching silicon. Optical elements including flexible diffraction gratings, mirrors, and lenses are provided, as are methods for forming optical devices and other articles using lithographic molding. A method for controlling the shape of a liquid on the surface of an article is provided, involving applying the liquid to a self-assembled monolayer on the surface, and controlling the electrical potential of the surface.

Patent
27 Nov 1998
TL;DR: In this paper, a first oxide layer is formed to protect the conductive structure, and an argon flow with a high speed of etching/deposition is provided to form a second oxide layer.
Abstract: A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide layer. While forming the second oxide layer a triangular or trapezium profile is formed due to an etching effect to the corner. An argon flow with a low speed of etching/deposition is provided to form a third oxide layer. The gap filling is completed.

Patent
06 Mar 1998
TL;DR: In this article, a chemical downstream etching (CDE) that is selective to silicon nitrides (SiN) over silicon oxide (SiO) was proposed, using at least one of a CH 3 F/CF 4 /O 2 recipe.
Abstract: A chemical downstream etching (CDE) that is selective to silicon nitrides (SiN) over silicon oxides (SiO) uses at least one of a CH 3 F/CF 4 /O 2 recipe and a CH 2 F 2 /CF 4 /O 2 recipe. Inflow rates are mapped for the respective components of the input recipe to find settings that provide both high nitride etch rates and high selectivity towards the SiN material. A pins-up scheme is used for simultaneously stripping away backside nitride with topside nitride.

Patent
23 Dec 1998
TL;DR: In this paper, a method comprising etching a material under plasma etching conditions using an etching composition which has a GWP of no greater than about 3000 and which comprises at least one etchant compound having a formula selected from the group consisting of FCO-CO-[(CR 1 R 2 ) m −CO] n −F and FCOCO-R 3 -CO-N −F, and wherein: m=0, 1, 2, 3, 4, or 5; n=1; R 1 & R 2 represent H, F or C
Abstract: A method comprising etching a material under plasma etching conditions using an etching composition which has a GWP of no greater than about 3000 and which comprises at least one etchant compound having a formula selected from the group consisting of F—CO—[(CR 1 R 2 ) m —CO] n —F and F—CO—R 3 —CO—F, and wherein: m=0, 1, 2, 3, 4, or 5; n=1; R 1 & R 2 represent H, F or C x H y F z ; wherein: x=1 or 2; and y+z=2x+1; R 3 represents CR 4 ═CR 5 , R 6 R 7 C═C or C≡C; wherein: R 4-7 represent H, F, or C x H y F z ; wherein: x=1 or 2; and y+z=2x+1; and also including the cleaning of a surface by use of an etchant compound, and further including an etching composition which includes said etchant compound and also an etchant-modifier.

Patent
19 Mar 1998
TL;DR: In this paper, a wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed.
Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a lower etching/depositing component ratio and thus a higher CMP removal rate; and (c) using a chemical mechanical process to remove at least a part of the second HDP-CVD layer using the first HDP-CVD layer as a stopper. A protective layer with the same etching/deposition components but a different ratio than the sacrificial layer can be deposited on the sacrificial layer to minimize the dishing effect during the initial stage of the chemical mechanical polishing process.

Journal ArticleDOI
TL;DR: In this paper, the authors presented a 2-dimensional (2-D) process simulation of a surface-micromachined capacitive ultrasonic transducers for both air and water applications.
Abstract: Surface-micromachined capacitive ultrasonic transducers, which are suitable for operation in both air and water, have been fabricated and tested. Amorphous silicon is used as a sacrificial layer because of its good etching selectivity versus a nitride membrane, and improved cell-size control is obtained by lithographic definition of cavity walls. In addition, appropriate feature designs based on two-dimensional (2-D) process simulations make it possible to achieve device cavity sealing with g-line optical lithography. Transmission experiments in both water and air are presented. A dynamic range in excess of 110 dB is observed in air at 2.3 MHz. In water, a single pair of transducers is able to operate from 2 to 15 MHz. When tuned, a 3.5-MHz tone burst results in a received signal with better than 60-dB signal-to-noise ratio (SNR). The transducer behaviour agrees with a theoretical understanding of transducer dynamics. The dynamic ranges achieved in this paper are the best reported to date for surface-micromachined capacitive ultrasonic transducers.

Journal ArticleDOI
TL;DR: In this article, a thin-film/silicon micromachined hybrid actuator is described, which relies on the flexure of a screen printed PZT layer on a silicon membrane (8 mm × 4 mm × 70 μm).
Abstract: A new silicon-based micropump is described in this paper. The key element of the device is a thick-film/silicon micromachined hybrid actuator. The actuation principle relies on the flexure of a screen printed piezoelectric lead zirconate titanate (PZT) layer on a silicon membrane (8 mm × 4 mm × 70 μm). An investigation into the deposition technology of the bottom electrode for the piezoelectric material showed that a gold resinate or Pt evaporated electrode on a 500 nm thick SiO 2 covered silicon wafer achieved best results for the membrane actuator. Inlet and outlet valves are of the cantilever type and use deep boron diffusion together with KOH etching. Pump rates of up to 120 μl min −1 have been achieved. A maximum backpressure of 2 kPa was measured when using a 600 V pp sinusoidal drive voltage at 200 Hz across a 100 μm thick PZT layer. The pump was compared with a conventional surface mounted piezoelectric driven micropump. The conventional pump achieves a performance which was a factor of 3–6 more efficient, but does not allow mass production.

Journal ArticleDOI
TL;DR: In this article, the authors measured surface roughness enhancement caused by Ar beam etching and investigated the relationship between roughness and bonding properties such as strength and interfacial voids.
Abstract: Using Ar beam etching in vacuum, strong bonding of Si wafers is attained at room temperature. With appropriate etching time, the bonding occurs spontaneously without any load to force two wafers together. However, surface roughness of the wafers increases during Ar beam etching. Because surface roughness has a strong influence on wafer bonding, long etching time degrades the bonding strength. Using atomic force microscope, we measured surface roughness enhancement caused by Ar beam etching, and investigated the relationship between surface roughness and bonding properties such as strength and interfacial voids. The results agree well with theoretical predictions using elastic theory and energy gain by bond formation. A guideline for successful room-temperature bonding is proposed from these results.

Patent
03 Apr 1998
TL;DR: In this paper, a micromechanical capacitive accelerometer is provided from a single silicon wafer, and the basic structure of the accelerometer was etched in the wafer to form a released portion in the substrate and the released and remaining portions of the substrate were coated with metal under conditions sufficient to form the micromachanical accelerometer, which can be used for airbag deployment, active suspension control, active steering control, anti-lock braking and other control systems requiring accelerometers having high sensitivity, extreme accuracy and resistance to out of plane forces.
Abstract: A micromechanical capacitive accelerometer is provided from a single silicon wafer. The basic structure of the micromechanical accelerometer is etched in the wafer to form a released portion in the substrate, and the released and remaining portions of the substrate are coated with metal under conditions sufficient to form a micromechanical capacitive accelerometer. The substrate is preferably etched using reactive-ion etching for at least the first etch step in the process that forms the basic structure, although in another preferred embodiment, all etching is reactive-ion etching. The accelerometer also may comprise a signal-conditioned accelerometer wherein signal-conditioning circuitry is provided on the same wafer from which the accelerometer is formed, and VLSI electronics may be integrated on the same wafer from which the accelerometer is formed. The micromechanical capacitive accelerometer can be used for airbag deployment, active suspension control, active steering control, anti-lock braking, and other control systems requiring accelerometers having high sensitivity, extreme accuracy and resistance to out of plane forces.

Patent
17 Mar 1998
TL;DR: In this article, a micromechanical capacitive accelerometer is provided from a single silicon wafer, and the basic structure of the accelerometer was etched in the wafer to form a released portion in the substrate and the released and remaining portions of the substrate were coated with metal under conditions sufficient to form the micromachanical accelerometer, which can be used for airbag deployment, active suspension control, active steering control, anti-lock braking and other control systems requiring accelerometers having high sensitivity, extreme accuracy and resistance to out of plane forces.
Abstract: A micromechanical capacitive accelerometer is provided from a single silicon wafer. The basic structure of the micromechanical accelerometer is etched in the wafer to form a released portion in the substrate, and the released and remaining portions of the substrate are coated with metal under conditions sufficient to form a micromechanical capacitive accelerometer. The substrate is preferably etched using reactive-ion etching for at least the first etch step in the process that forms the basic structure, although in another preferred embodiment, all etching is reactive-ion etching. The accelerometer also may comprise a signal-conditioned accelerometer wherein signal-conditioning circuitry is provided on the same wafer from which the accelerometer is formed, and VLSI electronics may be integrated on the same wafer from which the accelerometer is formed. The micromechanical capacitive accelerometer can be used for airbag deployment, active suspension control, active steering control, anti-lock braking, and other control systems requiring accelerometers having high sensitivity, extreme accuracy and resistance to out of plane forces.

Journal Article
TL;DR: Application of the silane bonding agent to the porcelain after hydrofluoric acid etching appeared to be suitable for achieving consistent bonding between the composite resin and the por Celcelain.
Abstract: The purpose of this study was to evaluate the effect of etching and silane priming on bond strength to a feldspathic porcelain (VMK 68) of a composite resin (Clearfil APX). Two hydrofluoric acid etchants (2.5% and 5%) and seven different etching times (0, 30, 60, 90, 120, 150, and 180 seconds) were used to etch the porcelain specimens respectively. A self-curing bonding agent containing a silane coupler (Clearfil Porcelain Bond) was used on both etched and unetched porcelain surfaces. Etched relief patterns were observed by means of a scanning electron microscope, and the bond strengths between the photocured composite resin and the porcelain were determined. Scanning electron micrographs revealed complicated etching patterns with increased etching time periods. Shear testing results showed that the bond strength to the unetched porcelain of the composite resin was very low, and that etching periods for more than 30 seconds effectively enhanced the bond strength. Of the two etching agents applied to the unsilanated porcelain, the buffered 2.5% etchant produced higher bond strengths than the 5% etchant for all etching time periods except for 180 seconds. Silane priming was effective and critical for improving bond strength to the porcelain. Application of the silane bonding agent to the porcelain after hydrofluoric acid etching appeared to be suitable for achieving consistent bonding between the composite resin and the porcelain.

Patent
28 Jul 1998
TL;DR: A chemical mechanical polishing composition and slurry comprising a composition capable of etching tungsten and at least one inhibitor of Tungsten etching was proposed in this paper.
Abstract: A chemical mechanical polishing composition and slurry comprising a composition capable of etching tungsten and at least one inhibitor of tungsten etching and methods for using the composition and slurry to polish tungsten containing substrates.

Journal ArticleDOI
TL;DR: The surface modification of natural MoS2 treated in an RF-oxygen plasma has been studied by X-ray photoelectron microscopy (XPS) as discussed by the authors, where the depth distribution of the component elements and their different possible combinations at or in the surfaces of the plasma etched samples is determined.

Patent
14 Jul 1998
TL;DR: In this article, the marginal portion of a semiconductor wafer is covered under a plasma sheath, so as to be out of contact with the wafer, thereby preventing it from being etched.
Abstract: An apparatus for subjecting a semiconductor wafer having an uncovered marginal portion, from which a photoresist film is removed, to an anisotropic etching. The apparatus comprises a process chamber which can be set to a vacuum. Upper and lower electrodes opposite to each other are provided in the process chamber. An etching gas is made into plasma between these electrodes. An electrostatic chuck is arranged on the lower electrode. A wafer is mounted on the electrostatic chuck. A ring made of dielectric material, movable upward and downward, is arranged between the electrodes. A central portion of the ring is formed as a hood having a recessed shape corresponding to the marginal portion of the wafer. During the etching, the hood covers the marginal portion of the wafer under a plasma sheath, so as to be out of contact with the wafer, thereby preventing the marginal portion of the wafer from being etched.

Journal ArticleDOI
TL;DR: In this paper, a room-temperature photoelectrochemical wet etching process was described that produces smoothly etched GaN surfaces using KOH solution and Hg arc lamp illumination.
Abstract: A room-temperature photoelectrochemical wet etching process is described that produces smoothly etched GaN surfaces using KOH solution and Hg arc lamp illumination. Atomic force microscope measurements indicate a root-mean-square etched surface roughness of 1.5 nm, which compares favorably to the unetched surface roughness of approximately 0.3 nm. Etch rates of 50 nm/min were obtained using a KOH solution concentration of 0.02 M and an illumination intensity of 40 mW/cm2. It is shown that the smooth etching occurs under conditions of low KOH solution concentration and high light intensities, which result in a diffusion-limited etch process.

Patent
Ashutosh Misra1
20 Aug 1998
TL;DR: In this paper, a method of cleaning a chemical vapor deposition processing chamber having deposits on an inner surface thereof is provided, which involves forming a plasma from one or more gases comprising a fluorine-containing but otherwise halogen-free non-global-warming compound, and contacting active species generated in the plasma with the inner surface of the chamber, with the proviso that the non-non-global warming compound is not trifluoroacetic anhydride.
Abstract: Provided is a novel method of cleaning a chemical vapor deposition processing chamber having deposits on an inner surface thereof is provided. The process involves forming a plasma from one or more gases comprising a fluorine-containing but otherwise halogen-free non-global-warming compound, and contacting active species generated in the plasma with the inner surface of the chamber, with the proviso that the non-global-warming compound is not trifluoroacetic anhydride. Also provided is a method of etching a layer on a silicon wafer. The method involves the steps of: (a) introducing a silicon wafer into a processing chamber, the silicon wafer comprising a layer to be etched; and (b) forming a plasma from one or more gases comprising a fluorine-containing but otherwise halogen-free non-global-warming compound. Active species generated in the plasma are contacted with the silicon wafer, thereby etching the layer, with the proviso that the non-global-warming compound is not trifluoroacetic anhydride. The chemistries in accordance with the invention provide environmentally benign alternatives to the conventionally used global-warming chemistries for chamber cleaning and semiconductor etching processes.

Patent
Tadashi Oshima1
25 Feb 1998
TL;DR: In this paper, a silicon nitride layer on a silicon layer or a silicon oxide layer is formed by loading the silicon or the silicon oxide layers and the silicon n-oxide layer in a dry etching atmosphere, and selectively etching the silicon polysilicon oxide layer with respect to the silicon and silicon oxide by flowing a fluorine gas consisting of any one of CH 2 F 2, CH 3 F, or CHF 3 and an inert gas.
Abstract: There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH 2 F 2 , CH 3 F, or CHF 3 and an inert gas to the dry etching atmosphere Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO 2 can be enhanced and also etching anisotropy can be enhanced

Journal ArticleDOI
TL;DR: A parametric study of the etching characteristics of 6H p+ and n+ SiC and thin-film SiC 0.5N0.5 in inductively coupled plasma (ICP) NF3/O2 and NF3 /Ar discharges has been performed as mentioned in this paper, where the etch rates in both chemistries increase monotonically with NF3 percentage and rf chuck power.
Abstract: A parametric study of the etching characteristics of 6H p+ and n+ SiC and thin-film SiC0.5N0.5 in inductively coupled plasma (ICP) NF3/O2 and NF3/Ar discharges has been performed. The etch rates in both chemistries increase monotonically with NF3 percentage and rf chuck power. The etch rates go through a maximum with increasing ICP source power, which is explained by a trade-off between the increasing ion flux and the decreasing ion energy. The anisotropy of the etched features is also a function of ion flux, ion energy and atomic fluorine neutral concentration. Indium-tin-oxide masks display relatively good etch selectivity over SiC (maximum of ∌70:1), while photoresist etches more rapidly than SiC. The surface roughness of SiC is essentially independent of plasma composition for NF3/O2 discharges, while extensive surface degradation occurs for SiCN under high NF3:O2 conditions. © 1998 American Vacuum Society.

Patent
05 Mar 1998
TL;DR: In this paper, an auxiliary electrode is provided at least on the upstream side of the base in a flow of electron current generated by the magnetic field applying means, including a local electrode arranged on the side facing the electrode II and means for adjusting impedance provided at a part of the local electrode to be electrically connected with the electrode I.
Abstract: A plasma etching device which has an auxiliary electrode enabling realization of a uniform plasma density of generated plasma on the surface of a base and which enables uniform etching with respect to the base without depending upon pressure and without rotating a magnetic field applying means. The plasma etching device has magnetic field applying means which has two parallel plate electrodes I and II and RF power applying means, with the base set on the electrode I, and which is horizontal and unidirectional with respect to the surface of the base where plasma etching is carried out. In this plasma etching device, an auxiliary electrode is provided at least on the upstream side of the base in a flow of electron current generated by the magnetic field applying means. The auxiliary electrode includes a local electrode arranged on the side facing the electrode II and means for adjusting impedance provided at a part of the local electrode to be electrically connected with the electrode I.