Showing papers on "Etching (microfabrication) published in 1999"

Step and flash imprint lithography: a new approach to high-resolution patterning

Abstract: An alternative approach to lithography is being developed based on a dual-layer imprint scheme. This process has the potential to become a high-throughput means of producing high aspect ratio, high-resolution patterns without projection optics. In this process, a template is created on a standard mask blank by using the patterned chromium as an etch mask to produce high-resolution relief images in the quartz. The etched template and a substrate that has been coated with an organic planarization layer are brought into close proximity. A low-viscosity, photopolymerizable formulation containing organosilicon precursors is introduced into the gap between the two surfaces. The template is then brought into contact with the substrate. The solution that is trapped in the relief structures of the template is photopolymerized by exposure through the backside of the quartz template. The template is separated from the substrate, leaving a UV-curved replica of the relief structure on the planarization layer. Features smaller than 60 nm in size have been reliably produced using this imprinting process. The resolution silicon polymer images are transferred through the planarization layer by anisotropic oxygen reactive ion etching. This paper provides a progress report on our efforts to evaluate the potential of this process.

Ultrahydrophobic polymer surfaces prepared by simultaneous ablation of polypropylene and sputtering of poly(tetrafluoroethylene) using radio frequency plasma

Abstract: Ultrahydrophobic polypropylene surfaces were prepared by the simultaneous etching of polypropylene and etching/sputtering of poly(tetrafluoroethylene) (PTFE) using inductively coupled radio frequency argon plasma. The semicrystalline polypropylene surface is roughened due to the differential rates at which the crystalline and amorphous regimes ablate and is also fluorinated by the fluorocarbon plasma that results from the ablation/depolymerization of PTFE. The roughness of the polypropylene is controlled by the time of plasma etching. The presence of PTFE increases the rate of polypropylene roughening by reactive ion etching. The resulting roughened and fluorinated polypropylene surfaces were characterized by water contact angle, X-ray photoelectron spectroscopy (XPS), scanning electron microscopy, and atomic force microscopy (AFM). Wettability was found to depend on the size scale and topology of the roughness. The most hydrophobic surfaces exhibited advancing and receding water contact angles of θA/θR =...

High-quality near-field optical probes by tube etching

Abstract: A method called tube etching for the fabrication of near-field optical probes is presented. Tip formation occurs inside a cylindrical cavity formed by the polymer coating of an optical fiber which is not stripped away prior to etching in hydrofluoric acid. The influence of temperature, etchant concentration, and fiber type on the tip quality is studied. A tip formation mechanism for the given geometry is proposed. The procedure overcomes drawbacks of the conventional etching techniques while still producing large cone angles: (i) tips with reproducible shapes are formed in a high yield, (ii) the surface roughness on the taper is drastically reduced, and (iii) the tip quality is insensitive to vibrations and temperature fluctuations during the etching process. After aluminum coating, optical probes with well-defined apertures are obtained. Due to the smooth glass surface the aluminum coating is virtually free of pinholes.

Fabrication of patterned media for high density magnetic storage

Abstract: Arrays of discrete, lithographically patterned magnetic elements have been proposed as a new generation of ultrahigh density patterned magnetic storage media. Interferometric lithography has been used to make prototype arrays over large areas with periods of 100–200 nm. Arrays of magnetic pillars, pyramids, and dots have been made by electrodeposition, evaporation and liftoff, and etching processes, and the magnetic properties of the particles and their mutual interactions have been measured.

Study of the SiO2-to-Si3N4 etch selectivity mechanism in inductively coupled fluorocarbon plasmas and a comparison with the SiO2-to-Si mechanism

Abstract: The mechanisms underlying selective etching of a SiO2 layer over a Si or Si3N4 underlayer, a process of vital importance to modern integrated circuit fabrication technology, has been studied. Selective etching of SiO2-to-Si3N4 in various inductively coupled fluorocarbon plasmas (CHF3, C2F6/C3F6, and C3F6/H2) was performed, and the results compared to selective SiO2-to-Si etching. A fluorocarbon film is present on the surfaces of all investigated substrate materials during steady state etching conditions. A general trend is that the substrate etch rate is inversely proportional to the thickness of this fluorocarbon film. Oxide substrates are covered with a thin fluorocarbon film (<1.5 nm) during steady-state etching and at sufficiently high self-bias voltages, the oxide etch rates are found to be roughly independent of the feedgas chemistry. The fluorocarbon film thicknesses on silicon, on the other hand, are strongly dependent on the feedgas chemistry and range from ∼2 to ∼7 nm in the investigated process...

The surface/bulk micromachining (SBM) process: a new method for fabricating released MEMS in single crystal silicon

Abstract: This paper presents the surface/bulk micromachining (SBM) process to allow fabricating released microelectromechanical systems using bulk silicon. The process starts with a [111]-oriented silicon wafer. The structural patterns are defined using the reactive ion etching technique used in surface micromachining. Then the patterns, as well as sidewalls, are passivated with an oxide film, and bare silicon is exposed at desired areas. The exposed bare silicon is further reactive ion etched, which defines sacrificial gap dimensions. The final release is accomplished by undercutting the exposed bulk silicon sidewalls in aqueous alkaline etchants. Because {111} planes are used as etch stops, very clean structural surfaces can be obtained. Using the SBM process, 5-, 10-, and 100-/spl mu/m-thick arbitrarily-shaped single crystal silicon structures, including comb-drive resonators, at 5-, 30-, and 100-/spl mu/m sacrificial gaps, respectively, are fabricated. An electrostatic actuation method using p-n junction isolation is also developed in this paper, and it is applied to actuate comb-drive resonators. The leakage current and junction capacitance of the reversed-biased p-n junction diodes are also found to be sufficiently small for sensor applications. The developed SBM process is a plausible alternative to the existing micromachining methods in fabricating microsensors and microactuators, with the advantage of using single crystal silicon.

Films doped with carbon for use in integrated circuit technology

Abstract: The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

Nanofabrication using a stencil mask

Abstract: We describe tests of a technique to fabricate nanostructures by the evaporation of metal through a stencil mask etched in a suspended silicon nitride membrane. Collimated evaporation through the mask gives metal dots less than 15 nm in diameter and lines 15–20 nm wide. We have investigated the extent of hole clogging and the factors which determine the ultimate resolution of the technique.

Raman microspectroscopy study of processing-induced phase transformations and residual stress in silicon

Abstract: Raman spectroscopy was used for analysis of phase transformations and residual stress in machined silicon. Wear debris from dicing of silicon was scanned with a Raman spectrometer. Recorded spectra manifest the presence of amorphous Si, hexagonal phase (Si-IV), bc8 phase (Si-III) and pristine Si-I under residual stress. On surfaces of diced wafers as well as lapped silicon wafers, the r8 phase (Si-XII) was detected in addition to the above phases. The composition of phases in diced cross sections of silicon wafers differs dramatically between high and low speed cuts. The quantification of these phases was attempted by curve fitting each spectrum with corresponding peaks of each phase. Subsequently, relative intensity maps of specific phases were generated. Thus, Raman spectroscopy studies of machined surfaces demonstrated metallization of Si under a variety of machining conditions including lapping, grinding, scratching, dicing and slicing. All metastable phases of silicon disappear after etching and polishing of respective wafers. No evidence of phase transformations was found on a quartz-damaged silicon wafer surface. Residual stress having a characteristic distribution was observed in this case.

Method for etching low k dielectrics

Abstract: The present disclosure pertains to a method for plasma etching of low k materials, particularly organic polymeric-based low k materials. The method employs an etchant plasma where the major etchant species are generated from a halogen other than fluorine and oxygen. The preferred halogen is chlorine. The volumetric (flow rate) or atomic ratio of the halogen: oxygen in the plasma source gas ranges from about 1:20 to about 20:1. When the halogen is chlorine, the preferred atomic ratio of chlorine: oxygen ranges from about 1:10 to about 5:1. When this atomic ratio for chlorine: oxygen is used, the etch selectivity for the low k material over adjacent oxygen-comprising or nitrogen-comprising layers is advantageous, typically in excess of about 10:1. The plasma source gas may contain additives in an amount of 15 % or less by volume which are designed to improve selectivity for the low k dielectric over an adjacent material, to provide a better etch profile, or to provide better critical dimension control, for example.

Fabrication ultra-thin bonded semiconductor layers

Abstract: The invention uses implantation, typically hydrogen implantation or implantation of hydrogen in combination with other elements, to a selected depth into a wafer with that contains one or more etch stops layers, treatment to split the wafer at this selected depth, and subsequent etching procedures to expose etch stop layer and ultra-thin material layer. A method for making an ultra-thin material layer bonded to a substrate, has the steps: (a) growing an etch stop layer on a first substrate; (b) growing an ultra-thin material layer on the etch stop layer; (c) implanting an implant gas to a selected depth into the first substrate; (d) bonding the ultra-thin material layer to a second substrate; (e) treating the first substrate to cause the first substrate to split at the selected depth; (f) etching remaining portion of first substrate to expose the etch stop layer, and (g) etching the etch stop layer to expose the ultra-thin material layer.

Patterning of highly oriented pyrolytic graphite by oxygen plasma etching

Abstract: Patterning of highly oriented pyrolytic graphite (HOPG) was demonstrated by oxygen plasma etching of lithographically patterned substrates. Periodic arrays of islands, or holes of several microns on an edge, were obtained on freshly cleaved HOPG surfaces which had been prepared with SiO2 mask stops and then oxygen plasma etched. The etching process is described, including a study of etch rate as a function of rf power, and morphology was characterized with scanning electron microscopy.

Method for etching a trench having rounded top and bottom corners in a silicon substrate

Abstract: The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.

Method for forming micro cavity

Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

Unconventional Methods for Fabricating and Patterning Nanostructures

Abstract: 4.1. Nanomachining with Scanning Probes 1831 4.2. Soft Lithography 1832 4.3. Embossing with Rigid Masters 1835 4.4. Near-Field Phase-Shifting Photolithography 1835 4.5. Topographically Directed Photolithography 1837 4.6. Topographically Directed Etching 1837 4.7. Lithography with Neutral Metastable Atoms 1838 4.8. Approaches to Size Reduction 1839 5. Techniques for Making Regular or Simple Patterns 1839

Vertical mirrors fabricated by deep reactive ion etching for fiber-optic switching applications

Abstract: We report on vertical mirrors fabricated by deep reactive ion etching of silicon. The mirror height is 75 /spl mu/m, covering the fiber core of a single-mode fiber when the latter is placed into a groove of equal depth and etched simultaneously with the mirror. To obtain a uniform etch depth, etching is stopped on a buried oxide layer. Using the buried oxide as a sacrificial layer allows to fabricate mirrors with suspension and actuation structures as well as fiber-alignment grooves in one and the same processing step. A minimal mirror thickness of 2.3 /spl mu/m was achieved, resulting in an aspect ratio higher than 30. The verticality was better than 89.3/spl deg/. In the upper part of the mirror a surface roughness below 40 nm rms was obtained. At a wavelength of 1300 nm the reflectivity of the aluminum-coated mirrors was measured to be higher than 76%. Using a reactive ion etched mirror we have fabricated an optical fiber switch with electrostatic actuation. The coupling loss in the bar state of two packaged prototypes was between 0.6 and 1.7 dB and between 1.4 and 3.4 dB in the cross state. The switching time is below 0.2 ms.

Microcontact Printing of Alkanephosphonic Acids on Aluminum: Pattern Transfer by Wet Chemical Etching

Abstract: Microcontact printing (μCP) has been used to pattern octadecanephosphonic acid on the native oxide surface film of aluminum supported on silicon or on silicon nitride-coated silicon wafers. The patterned alkanephosphonic acid protects the Al2O3/Al film from etching in a solution containing phosphoric, acetic, and nitric acids and water in a ratio of 16:1:1:2 and allows the nonpatterned film to be removed selectively. The patterned Al2O3/Al structures resulting from etching are continuous and electrically conductive within each pattern, and separated patterns are electrically isolated. Resistance measurements of the patterned structures are presented. Using μCP, Schottky diodes of aluminum have been prepared on p-type Si(100). The Schottky diodes exhibit rectifying behavior, and the forward-bias current−voltage (I−V) and reverse-bias capacitance−voltage (C−V) characteristics are presented.

Enhancement of silicon oxide etch rate and nitride selectivity using hexafluorobutadiene or other heavy perfluorocarbon

Abstract: A plasma etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. A primary fluorine-containing gas, preferably hexafluorobutadiene (C 4 F 6 ), is combined with a significantly larger amount of the diluent gas xenon (Xe) enhance nitride selectivity without the occurrence of etch stop. The chemistry is also useful for etching oxides in which holes and corners have already been formed, for which the use of xenon also reduces faceting of the oxide. For this use, the relative amount of xenon need not be so high. The invention may be used with related heavy fluorocarbons and other fluorine-based etching gases.

Post metalization chem-mech polishing dielectric etch

Abstract: A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer are then deposited within the patterned dielectric. A passivating layer is deposited on top of the conducting layer after the conducting layer has been planarized through chemical-mechanical polishing while simultaneously etching the dielectric layer through a process that does not damage the underlying conducting and liner layers. The insulating layer is preferably a dielectric such as silicon dioxide and the liner layer is tantalum, tantalum nitride or a combination of the two. The passivating layer preferably consists of carbon and fluorine bound up in various chemical forms. The conducting layer preferably consists of copper. Recipes for simultaneously forming the passivating layer and etching the dielectric layer, and for removing the passivating layer without damaging the underlying conducting and liner layers are provided.

High rate etching of SiC using inductively coupled plasma reactive ion etching in SF6-based gas mixtures

Abstract: Inductively coupled plasma (ICP) reactive ion etching of SiC was investigated using SF6 plasmas. Etch rates were studied as a function of substrate bias voltage (−3 to −500 V), ICP coil power (500–900 W), and chamber pressure (1–6 mT). The highest etch rate (970 nm/min) for SiC yet reported was achieved. Anisotropic etch profiles with highly smooth surfaces free of micromasking effects were obtained. The addition of O2 to the SF6 plasma was found to slightly increase the etch rate.

Characterization of silicon surface preparation processes for advanced gate dielectrics

Abstract: This paper gives a short overview of issues associated with the surface preparation of silicon surfaces for advanced gate dielectrics and the appearance and nature of the wafer surface after different chemical treatments. The main portion of the paper demonstrates the use of electrochemical open-circuit potential (OCP) measurements as a simple and powerful technique to investigate and characterize wet silicon surface-preparation processes. This technique provides unique information about the evolution of semiconductor surface reactions in wet- chemical environments and permits the investigation of the kinetics of oxidation and etching processes in situ and in real time. Very good agreement between results obtained by this technique and results from multiple internal reflection-Fourier transform infrared spectroscopy (MIR-FTIR), X-ray photoelectron spectroscopy (XPS), spectroscopic ellipsometry (SE), and contact-angle studies is presented in this paper. A model is also presented which permits the correlation of the measured open circuit potential difference to the thickness of a growing native oxide. The etching behavior of an ultrathin thermally grown silicon oxide layer in hydrofluoric acid (HF) is discussed as a new result obtained using the OCP technique.

Method for anisotropic plasma-chemical dry etching of silicon nitride layers using a gas mixture containing fluorine

Abstract: An etching gas mixture containing CHF3, SF6 and a non-oxidizing gas such as Ar is used as an etching gas mixture for the anisotropic plasma-chemical dry-etching of a silicon nitride layer differentially or selectively relative to a silicon oxide layer. The gas mixture does not contain oxygen, chlorine, bromine, iodine or halides in addition to the above mentioned constituents, so that the process can be carried out in reactor systems equipped with oxidizable electrodes. By adjusting the gas flow rates or composition ratios of CHF3, SF6, and argon in the etching gas mixture, it is possible to adjust the resulting etching selectivity of silicon nitride relative to silicon oxide, and the particular edge slope angle of the etched edge of the remaining silicon nitride layer. A high etch rate for the silicon nitride is simultaneously achieved.

Rapid evaluation of dislocation densities in n-type GaN films using photoenhanced wet etching

Abstract: We describe a technique based on photoelectrochemical wet etching that enables efficient and accurate evaluation of dislocation densities in n-type GaN films. The etching process utilizes dilute aqueous KOH solutions and Hg arc lamp illumination to produce etched GaN “whiskers” by selectively etching away material around threading dislocations. The etched whiskers, each corresponding to a single threading dislocation, can be effectively imaged by plan-view scanning electron microscopy. The distribution and density of dislocations are then readily observed over very large sample areas. Transmission electron microscope and atomic force microscope studies of the GaN samples confirm the accuracy of the dislocation density obtained by the wet etching.

Method for forming conductive line

Abstract: An improved method of forming a conductive line on a semiconductor substrate is described. A conductive layer is formed on the substrate. A patterned photoresist layer is formed on the conductive layer. A first etching step is performed on the conductive layer to define the conductive layer and to form a conductive line. A second etching step is performed on the conductive line to undercut the conductive line so as to make the conductive line have smaller bottom and to increase a distance between neighboring conductive lines. A third etching step is performed to remove residue generated on the substrate during the first and the second etching steps. A dielectric layer is formed to cover the conductive line. A planarization process is performed.

Plasma etching method

Abstract: PROBLEM TO BE SOLVED: To attain highly accurate plasma etching by controlling the transport process of a radical or reaction product mainly causing a microloading effect, or charge balance mainly causing the abnormality of an etching shape, especially a notch in gate etching. SOLUTION: Reaction gas supplied to a vacuum chamber is made into a plasma by a high frequency power 5 supplied to the vacuum chamber, and a sample 7 in the vacuum chamber is etched by a plasma 6 in this plasma etching method. Here, a bias power to be supplied to the sample 7 is pulse- modulated, or the reaction gas to be supplied is alternately switched and supplied. Also, at overetching of the sample 7 to be etched, the high frequency power 5 to be supplied is pulse-modulated.

Deep anisotropic etching of silicon

Abstract: We are interested in etching very deep anisotropic trenches (∼100 μm) with high aspect ratios (depth/width) (∼20–50) and high etch rates (∼5 μm/min). A high density plasma helicon reactor using SF6/O2 chemistry and a cryogenic chuck has been used for etching very narrow trenches from 1.2 to 10 μm wide on n-type Si wafers with a SiO2 mask. The first results show significant features that demonstrate the feasibility of this method. Two-micron-wide trenches have been etched to a depth of 80 μm at an average etch rate of 2.7 μm/min. The resulting profiles are highly anisotropic and selectivity of Si/SiO2 is remarkably high (>500).

Process for bonding micromachined wafers using solder

Abstract: A method by which semiconductor wafers (10, 12) can be solder bonded to form a semiconductor device, such as a sensor with a micromachined structure (14) The method entails forming a solderable ring (18) on the mating surface of a device wafer (10), such that the solderable ring (18) circumscribes the micromachine (14) on the wafer (10) A solderable layer (20, 26, 28) is formed on a capping wafer (12), such that at least the mating surface (24) of the capping wafer (12) is entirely covered by the solderable layer (20, 26, 28) The solderable layer (20, 26, 28) can be formed by etching the mating surface (24) of the capping wafer (12) to form a recess (16) circumscribed by the mating surface (24), and then forming the solderable layer (26) to cover the mating surface (24) and the recess (16) of the capping wafer (12) Alternatively, the solderable layer (28) can be formed by depositing a solderable material to cover the entire lower surface of the capping wafer (12), patterning the resulting solderable layer (28) to form an etch mask on the capping wafer (12), and then to form the recess (16), such that the solderable layer (28) covers the mating surface (24) but not the surfaces of the recess (16)

Bosch deep silicon etching: improving uniformity and etch rate for advanced MEMS applications

Abstract: Bosch deep silicon etching is nowadays widely used on inductive coupled plasma equipment. Most inductive plasma sources in the field consist of a coil of one or several turns wound around a dielectric vessel, which is powered by radio frequency to generate a high density plasma. Wafers are placed onto a substrate electrode downstream of the plasma source. RF self-biasing is applied to accelerate ions from the high density plasma towards the wafer. A major drawback of this kind of plasma source is its limited uniformity, which lowers the yield in critical MEMS applications. In this paper, we present an approach to improve etch uniformity by introducing an aperture construction between the plasma source and the wafer. In combination with balanced coil drive, excellent uniformity over 150 mm diameter wafers was achieved even at very high etch-rates.