Showing papers on "Etching (microfabrication) published in 2001"

The Science and Engineering of Microelectronic Fabrication

Abstract: PART I: OVERVIEW AND MATERIALS 1. An Introduction to Microelectronic Fabrication 1.1 Microelectronic Technologies -- A Simple Example 1.2 Unit Processes and Technologies 1.3 A Roadmap for the Course 1.4 Summary 2. Semiconductor Substrates 2.1 Phase Diagrams and Solid Solubility 2.2 Crystallography and Crystal Structure 2.3 Crystal Defects 2.4 Czochralski Growth 2.5 Bridgman Growth of GaAs 2.6 Float Zone Growth 2.7 Water Preparation and Specifications 2.8 Summary and Future Trends Problems References PART II: UNIT PROCESSING I: HOT PROCESSING AND ION IMPLANTATION 3. Diffusion 3.1 Fick's Diffusion Equation in One Dimension 3.2 Atomistic Models of Diffusion 3.3 Analytic Solutions of Fick's Law 3.4 Corrections to Simple Theory 3.5 Diffusion Coefficients for Common Dopants 3.6 Analysis of Diffused Profiles 3.7 Diffusion in SiO2 3.8 Diffusion Systems 3.9 SUPREM Simulations of Diffusion Profiles 3.10 Summary Problems References 4. Thermal Oxidation 4.1 The Deal-Grove Model of Oxidation 4.2 The Linear and Parabolic Rate Coeffients 4.3 The Initial Oxidation Regime 4.4 The Structure of SiO2 4.5 Oxide Characterization 4.6 The Effects of Dopants During Oxidation and Polysilicon Oxidation 4.7 Oxidation Induced Stacking Faults 4.8 Alternative Gate Insulations 4.9 Oxidation Sytems 4.10 SUPREM Oxidations 4.11 Summary Problems References 5. Ion Implantation 5.1 Idealized Ion Implantation Systems 5.2 Coulomb Scattering 5.3 Vertical Projected Range 5.4 Channeling and Lateral Projected Range 5.5 Implantation Damage 5.6 Shallow Junction Formation 5.7 Buried Dielectrics 5.8 Ion Implantation Systems -- Problems and Concerns 5.9 Implanted Profiles Using SUPREM+ 5.10 Summary Problems References 6. Rapid Thermal Processing 6.1 Gray Body Radiation, Heat Exchange, and Optical Absorption 6.2 High Density Optical Sources and Chamber Design 6.3 Temperature Measurement 6.4 Temperature Measurement 6.4 Thermoplastic Stress 6.5 Rapid Thermal Activation of Impurities 6.6 Rapid Thermal Processing of Dielectrics 6.7 Silicidation and Contact Formation 6.8 Alternative Rapid Thermal Processing Systems 6.9 Summary Problems References PART III: UNIT PROCESSES 2: PATTERN TRANSFER 7. Optical Lithography 7.1 Lithography Overview 7.2 Diffraction 7.3 The Modulation Transfer Function and Optical Exposures 7.4 Source Systems and Spatial Coherence 7.5 Contact/Proximity Printers 7.6 Projection Printers 7.7 Advanced Mask Concepts 7.8 Surface Reflections and Standing Waves 7.9 Alignment 7.10 Summary Problems References 8. Photoresists 8.1 Photoresist Types 8.2 Organic Materials and Polymers 8.3 Typical Reactions of DQN Positive Photoresist 8.4 Contrast Curves 8.5 The Critical Modulation Transfer Function 8.6 Applying and Developing Photoresist 8.7 Second Order Exposure Effects 8.8 Advanced Photoresists and Photoresist Processes 8.9 Summary Problems References 9. Nonoptical Lithographic Techniques 9.1 Interactions of High Energy Beams with Matter 9.2 Direct Write Electron Beam Lithography Systems 9.3 Direct Write Electron Beam Lithography Summary and Outlook 9.4 X-Ray Sources 9.5 Proximity X-Ray Exposure Systems 9.6 Membrane Masks 9.7 Projection X-Ray Lithography 9.8 Projection Electron Beam Lithography (SCALPEL) 9.9 E-bean and X-Ray Resists 9.10 Radiation Damage in MOS Devices 9.11 Summary Problems References PART IV: UNIT PROCESSES 3: THIN FILMS 10. Vacuum Science and Plasmas 10.1 The Kinetic Theory of Gasses 10.2 Gas Flow and Conductance 10.3 Pressure Ranges and Vacuum Pumps 10.4 Vacuum Seals and Pressure Measurement 10.5 The DC Glow Discharge 10.6 RF Discharges 10.7 High Density Plasmas 10.8 Summary Problems References 11. Etching 11.1 Wet Etching 11.2 Chemical Mechanical Publishing 11.3 Basic Regimes of Plasma Etching 11.4 High Pressure Plasma Etching 11.5 Ion Milling 11.6 Reactive Ion Etching 11.7 Damage in Reative Ion Etching 11.8 High Density Plasma (HDP) Etching 11.9 Liftoff 11.10 Summary Problems References 12. Physical Deposition: Evaporation and Sputtering 12.1 Phase Diagrams: Sublimation and Evaporation 12.2 Deposition Rates 12.3 Step Coverage 12.4 Evaporator Systems: Crucible Heating Techniques 12.5 Multicomponent Films 12.6 An Introduction to Sputtering 12.7 Physics of Sputtering 12.8 Deposition Rate: Sputter Yield 12.9 High Density Plasma Sputtering 12.10 Morphology and Step Coverage 12.11 Sputtering Methods 12.12 Sputtering of Specific Materials 12.13 Stress in Deposited Layers 12.14 Summary Problems References 13. Chemcial Vapor Deposition 13.1 A Simple CVD System for the Deposition of Silicon 13.2 Chemical Equilibrium and the Law of Mass Action 13.3 Gas Flow and Boundary Layers 13.4 Evaluation of the Simple CVD System 13.5 Atmospheric CVD of Dielectrics 13.6 Low Pressure CVD of Dielectrics and Semiconductors in Hot Wall Systems 13.7 Plasma Enhanced CVD of Dielectrics 13.8 Metal CVD + 13.9 Summary Problems References 14. Exiptaxial Growth 14.1 Water Cleaning and Native Oxide Removal 14.2 The Thermodynamics of Vapor Phase Growth 14.3 Surface Reactions 14.4 Dopant Incorporation 14.5 Defects in Epitaxial Growth 14.6 Slective Growth 14.7 Halide Transport GaAs Vapor Phase Epitaxy 14.8 Incommensurate and Strained Layer Heterooepitaxy 14.9 Metal Organic Chemical Vapor Deposition (MOCVD) 14.10 Advanced Silicon Vapor Phase Epitaxial Growth Techniques 14.11 Molecular Beam Epitaxy Technology 14.12 BCF Theory 14.13 Gas Source MBE and Chemical Beam Epitaxy 14.14 Summary Problems References PART V: PROCESS INTEGRATION 15. Device Isolation, Contacts, and Metallization 15.1 Junction and Oxide Isolation 15.2 LOCOAS Methods 15.3 Trench Isolation 15.4 Silicon on Insulator Isolation Techniques 15.5 Semi-insulating Substrates 15.6 Schottky Contacts 15.7 Implanted Ohmic Contacts 15.8 Alloyed Contacts 15.9 Multilevel Metallization 15.10 Planarization and Advanced Interconnect 15.11 Summary Problems References 16. CMOS Techniques 16.1 Basic Long Channel Device Behavior 16.2 Early MOS Technologies 16.3 The Basic 3 um Technology 16.4 Device Scaling 16.5 Hot Carrier Effects and Drain Engineering 16.6 Processing for Robust Oxides 16.7 Latchup 16.8 Shallow Source/Drains and Tailored Channel Doping 16.9 Summary Problems References 17. GaAs Technologies 17.1 Basic MESFET Operation 17.2 Basic MESFET Technology 17.3 Digital Technologies 17.4 MMC Technologies 17.5 MODFETs 17.6 Optoelectronic Devices 17.7 Summary Problems References 18. Silicon Bipolar Techniques 18.1 Review of Bipolar Devices -- Ideal and Quasi-ideal Behavior 18.2 Second Order Effects 18.3 Performance of BJTs 18.4 Early Bipolar Processes 18.5 Advaned Bipolar Processes 18.6 Hot Electron Effects in Bipolar Transitions 18.7 BiCMOS 18.8 Analog Bipolar Technolgies 18.9 Summary Problems References 19. MEMS (co-authored with G. Cibuzar, University of Minnesota) 19.1 Fundamentals of Mechanics 19.2 Stress in Thin Films 19.3 Mechanical to Electrical Transduction 19.4 Mechanics of Common MEMS Devices 19.5 Bulk Micromachining Etching Techniques 19.6 Bulk Micromachining Process Flow 19.7 Surface Micromachining Basics 19.8 Surface Micromachining Process Flow 19.9 MEMS Actuators 19.10 High Aspect Ratio Microsystems Technology (HARMST) 19.11 Summary Problems References 20. Integrated Circuit Manufacturing 20.1 Yield Prediction and Yield Tracking 20.2 Particle Control 20.3 Statistical Process Control 20.4 Full Factorial Experiments and ANOVA 20.5 Design of Experiments 20.6 Computer Integrated Manufacturing 20.7 Summary Problems References APPENDICES I. Acronyms and Common Symbols II. Properties of Selected Semiconductor Materials III. Physical Constants IV. Conversion Factors V. The Complimentary Error Function VI. F Values VII. SUPREM Commands Index

Femtosecond laser-assisted three-dimensional microfabrication in silica.

Abstract: We demonstrate direct three-dimensional (3-D) microfabrication inside a volume of silica glass. The whole fabrication process was carried out in two steps: (i) writing of the preprogrammed 3-D pattern inside silica glass by focused femtosecond (fs) laser pulses and (ii) etching of the written structure in a 5% aqueous solution of HF acid. This technique allows fabrication of 3-D channels as small as 10 μm in diameter inside the volume with any angle of interconnection and a high aspect ratio (10‐μm-diameter channels in a 100‐μm-thick silica slab).

Anisotropic etching of silicon in TMAH solutions

Abstract: Anisotropic etching characteristics of tetramethyl ammonium hydroxide (TMAH) such as the dependences of the etching rates of (100), (110) and (111) crystal planes on temperature and concentration, the selectivity to SiO 2 and Si 3 N 4 , electrochemical etching characteristics, aluminum etching rate dependences on pH and conductivity and the effect of potassium ion addition are reviewed. Furthermore, the preliminary results obtained by the approach using a molecular orbital program are briefly introduced.

Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication

Abstract: We combine a self-organizing diblock copolymer system with semiconductor processing to produce silicon capacitors with increased charge storage capacity over planar structures. Our process uses a diblock copolymer thin film as a mask for dry etching to roughen a silicon surface on a 30 nm length scale, which is well below photolithographic resolution limits. Electron microscopy correlates measured capacitance values with silicon etch depth, and the data agree well with a geometric estimate. This block copolymer nanotemplating process is compatible with standard semiconductor processing techniques and is scalable to large wafer dimensions.

Integrated low k dielectrics and etch stops

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects

Method of forming vias in silicon carbide and resulting devices and circuits

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Porous Silicon as a Versatile Platform for Laser Desorption/Ionization Mass Spectrometry

Abstract: Desorption/ionization on porous silicon mass spectrometry (DIOS-MS) is a novel method for generating and analyzing gas-phase ions that employs direct laser vaporization. The structure and physicochemical properties of the porous silicon surfaces are crucial to DIOS-MS performance and are controlled by the selection of silicon and the electrochemical etching conditions. Porous silicon generation and DIOS signals were examined as a function of silicon crystal orientation, resistivity, etching solution, etching current density, etching time, and irradiation. Pre- and postetching conditions were also examined for their effect on DIOS signal as were chemical modifications to examine stability with respect to surface oxidation. Pore size and other physical characteristics were examined by scanning electron microscopy and Fourier transform infrared spectroscopy, and correlated with DIOS-MS signal. Porous silicon surfaces optimized for DIOS response were examined for their applicability to quantitative analysis, ...

Selective etching of GaN polar surface in potassium hydroxide solution studied by x-ray photoelectron spectroscopy

Abstract: Etching characteristics of nondoped GaN films with the polar surface in KOH solution have been investigated. It is confirmed that the continuous etching in KOH solution takes place only for the GaN films with N-face (−c) polarity independent of the deposition method and growth condition. It is found by x-ray photoelectron spectroscopy (XPS) analysis for the Ga face (+c) and N-face (−c) GaN films that the atomic composition of the +c surface is not changed before and after dipping in KOH solution and that on the other hand, the amount of oxygen (oxide) on the −c surface is significantly decreased by the etching. It is also found that the band bending increases by −0.4±0.2 and 0.6±0.2 eV for the +c and −c surfaces after etching, respectively. This is discussed in terms of the surface chemistry. Based on the XPS result, the selective etching of the GaN polar surface is pointed out to originate from bonding configuration of nitrogen at the surface.

Method of manufacturing a semiconductor device

Abstract: A method of manufacturing a semiconductor device having a microminiture trench isolation in which an insulating film is embedded by an HDP-CVD method comprising: a step of pre-planarization by conducting a dry etching selectively with respect to the insulating film laminated excessively on the surface of substrate, which is to be an active region, and a step of polishing by a CMP method in order to improve a surface planarity of the insulating film, wherein an etching mask used at the time of opening a trench opening portion has a multi-layer structure including a silicon nitride film and a polycrystal silicon film; the polycrystal silicon film is used as an etching stopper at the time of pre-planarization; and the silicon nitride film is used as an etching stopper at the time of polishing by a CMP method in order to remove simultaneously the excessive insulating film and the polycrystal silicon film to expose and a surface of the substrate, which is the active region, whereby the trench isolation having a satisfactory shape is obtainable.

100 nm period silicon antireflection structures fabricated using a porous alumina membrane mask

Abstract: An ordered anodic porous alumina membrane has been used as a lithographic mask of SF6 fast atom beam etching to generate a 100 nm period antireflection structure on a silicon substrate. The antireflection structure consists of a deep hexagonal grating with 100 nm period and aspect ratio of 12, which is a fine two-dimensional antireflection structure. In the wavelength region from 400 to 800 nm, the reflectivity of the silicon surface decreases from around 40% to less than 1.6%. The measured results are explained well with the theoretical results calculated on the basis of rigorous coupled-wave analysis.

A fast prototyping process for fabrication of microfluidic systems on soda-lime glass

Abstract: This paper describes a fast, low-cost but reliable process for the fabrication of microfluidic systems on soda-lime glass substrates. Instead of using an expensive metal or polisilicon/nitride layer as an etch mask, a thin layer of AZ 4620 positive photoresist (PR) is used for buffered oxide etching (BOE) of soda-lime glass. A novel two-step baking process prolongs the survival time of the PR mask in the etchant, which avoids serious peeling problems of the PR. A new process to remove precipitated particles generated during the etching process is also reported in which the glass substrate is dipped into a 1 M hydrochloride solution. A microfluidic channel with a depth of 35.95±0.39 µm is formed after 40 min BOE in an ultrasonic bath. The resulting channel has a smooth profile with a surface roughness of less than 45.95±7.96 A. Glass chips with microfluidic channels are then bonded at 580 °C for 20 min to seal the channel while a slight pressure is applied. A new bonding process has been developed such that the whole process can be finished within 10 h. To our knowledge, this is the shortest processing time that has ever been reported. In the present study, an innovative microfluidic device, a `micro flow-through sampling chip', has been demonstrated using the fabrication method. Successful sampling and separation of Cy5-labelled bovine serum albumin (BSA) and anti-BSA has been achieved. This simple fabrication process is suitable for fast prototyping and mass production of microfluidic systems.

Deep reactive ion etching of Pyrex glass using SF6 plasma

Abstract: Deep reactive ion etching of Pyrex glass has been characterized in sulfur hexafluoride plasma (SF6). High etch rate (∼0.6 μm/min) was demonstrated under a condition of low pressure (0.2 Pa) and high self-bias (−390 V) by using a magnetically enhanced inductively coupled plasma reactive ion etching. Vertical etch profile (taper angle ∼88°), high aspect ratio (>10) and through-wafer etching of Pyrex glass (200 μm in thickness) were achieved under the condition by using thick (20 μm) and vertical electroplated nickel film as mask. The vertical etch profile was achieved when the mask opening is narrower than 20 μm because the deposition of nonvolatile product on the sidewall is reduced. A novel etching technique “scoop-out etching” was demonstrated by using the present etching characteristics.

Two etchant etch method

Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

The effect of isopropyl alcohol on etching rate and roughness of (1 0 0) Si surface etched in KOH and TMAH solutions

Abstract: The etching process of (1 0 0) silicon wafers in KOH and TMAH solutions with isopropyl alcohol (IPA) has been studied. The etching rates of different crystallographic planes in the wide range of solutions concentration have been estimated. The mutual relations of the etching rates of these planes have been analysed. Special emphasis was put on the roughness of silicon surface obtained in effect of etching. It was proved that IPA added to the solution improves the morphology of resulted surface. Detailed indications about the solution composition, ensuring satisfactory surface quality have been given. On the basis of experimental results and theoretical considerations, some attempts were made to explain the etching behaviour of silicon in KOH and TMAH solutions with IPA addition. It was suggested that TMA+ ions play similar role in the solution to IPA particles and participate in smoothening of the etched surface.

Optical gain at 1.54 μm in erbium-doped silicon nanocluster sensitized waveguide

Abstract: Optical gain at 1.54 μm in erbium-doped silicon-rich silicon oxide (SRSO) is demonstrated. Er-doped SRSO thin film was fabricated by electron-cyclotron resonance enhanced chemical vapor deposition of silicon suboxide with concurrent sputtering of erbium followed by a 5 min anneal at 1000 °C. Ridge-type single mode waveguides were fabricated by wet chemical etching. Optical gain of 4 dB/cm of an externally coupled signal at 1.54 μm is observed when the Er is excited via carriers generated in the Si nanoclusters by the 477 nm line of an Ar laser incident on the top of the waveguide at a pump power of 1.5 W cm−2.

Method of forming smaller contact size using a spacer hard mask

Abstract: An exemplary method of forming contact holes includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.

Composite interposer and method for producing a composite interposer

Abstract: A composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers. A method for fabricating a composite interposer comprising disposing a silicon layer on a substrate, and selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate. Vias are formed through the exposed part of the substrate. The method additionally includes filling the vias and the silicon openings with a filler material (e.g., a high-aspect-ratio-capable photodefinable epoxy polymer) to form filled silicon openings and filled vias, forming first openings through the filled silicon openings and through the filled vias, forming second opening through filler material to expose semiconductor devices on the silicon layer, and interconnecting electrically, through the first openings and through the second openings, the exposed semiconductor devices with pads disposed against a bottom of the substrate.

Silicon micromachining using a high-density plasma source

Abstract: Dry etching of Si is critical in satisfying the demands of the micromachining industry. The micro-electro-mechanical systems (MEMS) community requires etches capable of high aspect ratios, vertical profiles, good feature size control and etch uniformity along with high throughput to satisfy production requirements. Surface technology systems' (STS's) high-density inductively coupled plasma (ICP) etch tool enables a wide range of applications to be realized whilst optimizing the above parameters. Components manufactured from Si using an STS ICP include accelerometers and gyroscopes for military, automotive and domestic applications. STS's advanced silicon etch (ASETM) has also allowed the first generation of MEMS-based optical switches and attenuators to reach the marketplace. In addition, a specialized application for fabricating the next generation photolithography exposure masks has been optimized for 200 mm diameter wafers, to depths of ~750 µm. Where the profile is not critical, etch rates of greater than 8 µm min-1 have been realized to replace previous methods such as wet etching. This is also the case for printer applications. Specialized applications that require etching down to pyrex or oxide often result in the loss of feature size control at the interface; this is an industry wide problem. STS have developed a technique to address this. The rapid progression of the industry has led to development of the STS ICP etch tool, as well as the process.

Guide to references on III–V semiconductor chemical etching

Abstract: The literature on chemical etching of III–V semiconductors is reviewed with the intent to organize citations in categories useful to device and materials investigators. Descriptive citations are grouped by the intended etch application and subgrouped by specific semiconductors for both wet and dry etching. A separate section groups citations by the various chemical compositions used as etchants so that a broad view of results and issues can be accessed. The final section lists references by author, with complete titles and notes of their relevance to etching.

Method of plasma etching of silicon carbide

Abstract: The invention provides a process for plasma etching silicon carbide with selectivity to an overlapping and/or underlying dielectric layer of material. The etching gas includes a hydrogen-containing fluorocarbon gas such as CH 3 F, an oxygen-containing gas such as O 2 and an optional carrier gas such as Ar. The dielectric material can comprise silicon dioxide, silicon nitride, silicon oxynitride or various low-k dielectric materials including organic low-k materials. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrates.

Single-crystal aluminum nitride nanomechanical resonators

Abstract: Aluminum nitride is a light, stiff, piezoelectrically active material that can be epitaxially grown on single-crystal Si. AlN is beginning to play a role in the integration of semiconducting electronic and surface acoustic wave devices, and may prove useful for the integration of other types of mechanical devices as well. We describe the growth and subsequent electron-beam patterning and etching of epitaxial AlN-on-silicon films into nanomechanical flexural resonators. We have measured resonators with fundamental mechanical resonance frequencies above 80 MHz, and quality factors in excess of 20 000.

Process for selectively etching dielectric layers

Abstract: A method is provided for etching a dielectric structure. The dielectric structure comprises: (a) a layer of undoped silicon oxide or F-doped silicon oxide; and (b) a layer of C,H-doped silicon oxide. The dielectric structure is etched in a plasma-etching step, which plasma-etching step is conducted using a plasma source gas that comprises nitrogen atoms and fluorine atoms. As one example, the plasma source gas can comprise a gaseous species that comprises one or more nitrogen atoms and one or more fluorine atoms (e.g., NF3). As another example, the plasma source gas can comprise (a) a gaseous species that comprises one or more nitrogen atoms (e.g., N2) and (b) a gaseous species that comprises one or more fluorine atoms (e.g., a fluorocarbon gas such as CF4). In this etching step, the layer of C,H-doped silicon oxide is preferentially etched relative to the layer of undoped silicon oxide or F-doped silicon oxide. The method of the present invention is applicable, for example, to dual damascene structures.

Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

Abstract: A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.

Use of ammonia for etching organic low-k dielectrics

Abstract: Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.

Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures

Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically the oxide is selected from silicon oxide, silicon oxynitride, tantalum oxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) of chemical vapor deposition (CVD). In particular, an initial etch chemistry, used during the majority of the tungsten or tungsten nitride etching process (the main etch), employs the use of a plasma source gas where the chemically functional etchant species are generated from a combination of sulfur hexaflouride (SF6) and nitrogen (N2), or in the alternative, from a combination of nitrogen trifluoride (NF3), chlorine (Cl2) and carbon tetrafluoride (CF4). Toward the end of the main etching process, a second chemistry is used in which the chemically functional etchant species are generated from Cl2 and O2. This final portion of the etch process may be referred to as an 'overetch' process, since etching is carried out to at least the surface underlying the tungsten or tungsten nitride. However, this second etch chemistry may optionally be divided into two steps, where the plasma source gas oxygen content and plasma source power are increased in the second step.

Investigations of surface reactions during C2F6 plasma etching of SiO2 with equipment and feature scale models

Abstract: During fluorocarbon plasma etching of SiO2, a polymer passivation layer is generally deposited on the surface of the wafer The polymer layer regulates the etch by limiting the availability of activation energy and reactants, and providing the fuel for removal of oxygen To investigate these processes, a surface reaction mechanism for fluorocarbon plasma etching of SiO2 has been developed The mechanism describes the polymerization process as resulting from neutral sticking, ion sputtering, F atom etching, and low-energy ion assisted deposition The etch mechanism is a multistep passivation process which results in consumption of both the polymer and the wafer The surface mechanism was incorporated into an equipment scale simulator to investigate the properties of SiO2 etching in an inductively coupled C2F6 discharge, and predicts that the SiO2 etch rate saturates at high substrate biases due to the depletion of passivation Experimental results for SiO2 etch rates and selectivity of SiO2 over Si as a fu

Method of forming ultrathin oxide layer

Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permittivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used. Two or more of the HF etching, surface termination, oxidation, hydroxyl replacement of the surface termination and deposition on the oxide can be conducted in situ.

Using hydrogen gas in a post-etch radio frequency-plasma contact cleaning process

Abstract: Provided is a method for removing etch byproducts inside a contact hole while minimizing lateral etching of the contact hole. After an etching process, a wafer having a contact hole is placed inside a plasma reaction chamber. The contact hole contains etch byproducts that may degrade the quality of electrical connections. A radio frequency (RF) source creates a RF field inside the reaction chamber. A gas mixture containing chemicals that are reactive with the etch byproducts is introduced into the reaction chamber. The gas mixture becomes ionized by the RF field and reacts with the etch byproducts in the contact hole, removing the etch byproducts. The gas mixture may include approximately 10-60 vol. % hydrogen gas, a gas that reacts with the etch byproducts (e.g., NF 3 ), and nitrogen. The hydrogen gas at least significantly reduces lateral etching of the contact hole by the reactive gas.

Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device

Abstract: To improve a shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15 b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15 b) of the gate electrode 15G.

Strain-driven self-positioning of micromachined structures

Abstract: We introduce a method to make self-positioned micromachined structures by using the strain in a pair of lattice-mismatched epitaxial layers. This method allows the fabrication of simple and robust hinges for movable parts, and it can be applied to any pair of lattice-mismatched epitaxial layers, in semiconductors or metals. As an application example, a standing mirror was fabricated. A multilayer structure including an AlGaAs/GaAs dielectric mirror and an InGaAs strained layer was grown by molecular-beam epitaxy on a GaAs substrate. After releasing the multilayer structure from the substrate by selective etching, it moved to its final position powered by the strain release in the InGaAs layer.