Showing papers on "Etching (microfabrication) published in 2002"

Fundamentals of microfabrication : the science of miniaturization

Abstract: LITHOGRAPHY Introduction Historical Note: Lithography's Origins Photolithography Overview Critical Dimension, Overall Resolution, Line-Width Lithographic Sensitivity and Intrinsic Resist Sensitivity (Photochemical Quantum Efficiency) Resist Profiles Contrast and Experimental Determination of Lithographic Sensitivity Resolution in Photolithography Photolithography Resolution Enhancement Technology Beyond Moore's Law Next Generation Lithographies Emerging Lithography Technologies PATTERN TRANSFER WITH DRY ETCHING TECHNIQUES Introduction Dry Etching: Definitions and Jargon Plasmas or Discharges Physical Etching: Ion Etching or Sputtering and Ion-Beam Milling Plasma Etching (Radical Etching) Physical/Chemical Etching PATTERN TRANSFER WITH ADDITIVE TECHNIQUES Introduction Silicon Growth Doping of Si Oxidation of Silicon Physical Vapor Deposition Chemical Vapor Deposition Silk-Screening or Screen-Printing Sol-Gel Deposition Technique Doctors' Blade or Tape Casting Plasma Spraying Deposition and Arraying Methods of Organic Layers in BIOMEMS Thin versus Thick Film Deposition Selection Criteria for Deposition Method WET BULK MICROMACHINING Introduction Historical Note Silicon Crystallography Silicon As Substrate Silicon As A Mechanical Element In MEMS Wet Isotropic And Anisotropic Etching Alignment Patterns Chemical Etching Models Etching With Bias And/Or Illumination Of The Semiconductor Etch-Stop Techniques Problems With Wet Bulk Micromachining SURFACE MICROMACHINING Introduction Historical Note Mechanical Properties of Thin Films Surface Micromachining Processes Poly-Si Surface Micromachining Modifications Non-Poly-Si Surface Micromachining Modifications Materials Case Studies LIGA AND MICROMOLDING Introduction LIGA-Background LIGA and LIGA-Like Process Steps A COMPARISON OF MINIATURIZATION TECHNIQUES: TOP-DOWN AND BOTTOM-UP MANUFACTURING Introduction Absolute and Relative Tolerance in Manufacturing Historical Note: Human Manufacturing Section I: Top-Down Manufacturing Methods Section II: Bottom-Up Approaches MODELING, BRAINS, PACKAGING, SAMPLE PREPARATION AND NEW MEMS MATERIALS Introduction Modeling Brains In Miniaturization Packaging Substrate Choice SCALING, ACTUATORS, AND POWER IN MINIATURIZED SYSTEMS Introduction Scaling Actuators Fluidics Scaling In Analytical Separation Equipment Other Actuators Integrated Power MINIATURIZATION APPLICATIONS Introduction Definitions and Classification Method Decision Three OVERALL MARKET For MICROMACHINES Introduction Why Use Miniaturization Technology ? From Perception to Realization Overall MEMS Market Size MEMS Market Character MEMS Based on Si Non-Silicon MEMS MEMS versus Traditional Precision Engineering The Times are a'Changing APPENDICES Metrology Techniques WWW Linkpage Etch Rate for Si, SiO2 Summary of Top-Down Miniaturization Tools Listing of names of 20 amino acids & their chemical formulas Genetic code Summary of Materials and Their Properties for Microfabrication References for Detailed Market Information on Miniature Devices MEMS Companies Update Suggested Further Reading Glossary Symbols used in Text INDEX Each chapter also contains sections of examples and problems

Ultrafast and direct imprint of nanostructures in silicon

Abstract: The fabrication of micrometre- and nanometre-scale devices in silicon typically involves lithography and etching. These processes are costly and tend to be either limited in their resolution or slow in their throughput1. Recent work has demonstrated the possibility of patterning substrates on the nanometre scale by ‘imprinting’2,3 or directed self-assembly4, although an etching step is still required to generate the final structures. We have devised and here demonstrate a rapid technique for patterning nanostructures in silicon that does not require etching. In our technique—which we call ‘laser-assisted direct imprint’ (LADI)—a single excimer laser pulse melts a thin surface layer of silicon, and a mould is embossed into the resulting liquid layer. A variety of structures with resolution better than 10 nm have been imprinted into silicon using LADI, and the embossing time is less than 250 ns. The high resolution and speed of LADI, which we attribute to molten silicon's low viscosity (one-third that of water), could open up a variety of applications and be extended to other materials and processing techniques.

Nanostructuring surfaces by ion sputtering

Abstract: Surface etching by ion sputtering can be used to pattern surfaces. Recent studies using the high-spatial-resolution capability of the scanning tunnelling microscope revealed in fact that ion bombardment produces repetitive structures at nanometre scale, creating peculiar surface morphologies ranging from self-affine patterns to `fingerprint'-like and even regular structures, for instance waves (ripples), chequerboards or pyramids. The phenomenon is related to the interplay between ion erosion and diffusion of adatoms (vacancies), which induces surface re-organization. The paper reviews the use of sputter etching to modify `in situ' surfaces and thin films, producing substrates with well defined vertical roughness, lateral periodicity and controlled step size and orientation.

Current sensor, its production substrate, and its production process

Abstract: A new current sensor, its production substrate, and its production process, wherein the surface layer of the substrate is made of the thin film of low temperature coefficient of resistivity such as nickel-copper alloy, manganese-copper alloy or nickel-chromium alloy, it is tightly adhered onto the thin plates of ceramic, aluminum oxide, aluminum nitride or Beryllium dioxide (BeO) to form a new substrate by a hot-press laminating; next, by optical mask etching, the pattern of current sensor are formed on the surface of the substrate; and the flip-chip is formed on the lateral electrodes in the bottom of the current sensor unit, and the front electrodes are plated to increase the thickness; then, the pattern are modified with laser to obtain the pattern of sensor with precise and constant resistivity; after that, and the pattern of a sensor are coated with a protection layer; and the substrate is segmented, and is plated on the end face electrode 60 by sputtering; finally, a single and small chip-scaled current sensor is obtained by dicing and barrel plating.

Method for forming multiple structures in a semiconductor device

Abstract: A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures.

Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching (DRIE)

Abstract: The ability to predict and control the influence of process parameters during silicon etching is vital for the success of most MEMS devices. In the case of deep reactive ion etching (DRIE) of silicon substrates, experimental results indicate that etch performance as well as surface morphology and post-etch mechanical behavior have a strong dependence on processing parameters. In order to understand the influence of these parameters, a set of experiments was designed and performed to fully characterize the sensitivity of surface morphology and mechanical behavior of silicon samples produced with different DRIE operating conditions. The designed experiment involved a matrix of 55 silicon wafers with radius hub flexure (RHF) specimens which were etched 10 min under varying DRIE processing conditions. Data collected by interferometry, atomic force microscopy (AFM), profilometry, and scanning electron microscopy (SEM), was used to determine the response of etching performance to operating conditions. The data collected for fracture strength was analyzed and modeled by finite element computation. The data was then fitted to response surfaces to model the dependence of response variables on dry processing conditions.

Guidelines for etching silicon MEMS structures using fluorine high-density plasmas at cryogenic temperatures

Abstract: This paper presents guidelines for the deep reactive ion etching (DRIE) of silicon MEMS structures, employing SF/sub 6//O/sub 2/-based high-density plasmas at cryogenic temperatures. Procedures of how to tune the equipment for optimal results with respect to etch rate and profile control are described. Profile control is a delicate balance between the respective etching and deposition rates of a SiO/sub x/F/sub y/ passivation layer on the sidewalls and bottom of an etched structure in relation to the silicon removal rate from unpassivated areas. Any parameter that affects the relative rates of these processes has an effect on profile control. The deposition of the SiO/sub x/F/sub y/ layer is mainly determined by the oxygen content in the SF/sub 6/ gas flow and the electrode temperature. Removal of the SiO/sub x/F/sub y/ layer is mainly determined by the kinetic energy (self-bias) of ions in the SF/sub 6//O/sub 2/ plasma. Diagrams for profile control are given as a function of parameter settings, employing the previously published "black silicon method". Parameter settings for high rate silicon bulk etching, and the etching of micro needles and micro moulds are discussed, which demonstrate the usefulness of the diagrams for optimal design of etched features. Furthermore, it is demonstrated that in order to use the oxygen flow as a control parameter for cryogenic DRIE, it is necessary to avoid or at least restrict the presence of fused silica as a dome material, because this material may release oxygen due to corrosion during operation of the plasma source. When inert dome materials like alumina are used, etching recipes can be defined for a broad variety of microstructures in the cryogenic temperature regime. Recipes with relatively low oxygen content (1-10% of the total gas volume) and ions with low kinetic energy can now be applied to observe a low lateral etch rate beneath the mask, and a high selectivity (more than 500) of silicon etching with respect to polymers and oxide mask materials is obtained. Crystallographic preference etching of silicon is observed at low wafer temperature (-120/spl deg/C). This effect is enhanced by increasing the process pressure above 10 mtorr or for low ion energies (below 20 eV).

Etching of Colloidal InP Nanocrystals with Fluorides: Photochemical Nature of the Process Resulting in High Photoluminescence Efficiency

Abstract: The photoluminescence efficiency of InP nanocrystals prepared via the dehalosilylation reaction between indium chloride and tris-(trimethylsilyl)phosphine in mixtures of trioctylphosphine and trioctylphosphine oxide can be drastically improved by etching with fluorine compounds, as proposed several years ago by Micic et al. A systematic study reported in this communication revealed the pure photochemical nature of this etching process and allowed to improve considerably its reproducibility and reliability. Applying the HF treatment in combination with size-selective photoetching allows to vary the mean size of InP nanocrystals from ∼1.7 nm to 6.5 nm, resulting in monodisperse colloids with band-edge luminescence tunable from green to near-IR and room-temperature quantum yields in the range of 20−40%.

Two-dimensional lateral superlattices of nanostructures: Nonlithographic formation by anodic membrane template

Abstract: A nonlithographic technique that utilizes highly ordered anodized aluminum oxide porous membrane as template is presented as a general fabrication means for the formation of an array of vastly different two-dimensional lateral superlattices structures. Hexagonal close-packed nanopore arrays were fabricated on Si, GaAs, and GaN substrates via reactive ion etching. Quantum dot arrays of various metals and semiconductors were formed through evaporation and subsequent etching. The two-dimensional lateral superlattice structures fabricated using this method are of a high level of ordering, uniformity, and packing density. The diameter and periodicity of the nanostructures are determined by the features of the original alumina membrane, which can be adjusted by varying the anodization conditions.

High density plasma CVD process for gapfill into high aspect ratio features

Abstract: A method of depositing a film on a substrate disposed in a substrate processing chamber. In one embodiment the method includes depositing a first portion of the film to at partially fill a gap formed between to adjacent features formed on the substrate. The first portion of film is deposited using a high density plasma formed from a first gaseous mixture flown into the process chamber. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step and a subsequent chemical etch step. The physical etch step sputter etches the first portion of film by forming a plasma from a sputtering agent introduced into the processing chamber and biasing the plasma towards the substrate. After the physical etching step, the film is chemically etched by forming a plasma from a reactive etchant gas introduced into the processing chamber. After the etching sequence is complete and entry to the gap has been widened, a second portion of the film is deposited over the first portion to further fill the gap by forming a high density plasma from a second gaseous mixture flown into the process chamber.

Etch process for dielectric materials comprising oxidized organo silane materials

Abstract: The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016) and wider trenches. The technique is also suitable for forming dual damascene structures In additional embodiments, manufacturing systems are provided for fabricating IC structures of the present invention. These systems include a controller that is adapted for interacting with a plurality of fabricating stations.

Dynamic etching of silicon for broadband antireflection applications

Abstract: An electrochemical etching technique has been developed that provides continuous control over the porosity of a porous silicon layer as a function of etching depth. Thin films with engineered porosity gradients, and thus a controllable gradient in the index of refraction, have been used to demonstrate broadband antireflection properties on silicon wafer and solar cell substrates. A simulation was also developed to examine the effects of specific porosity profiles on film reflectivity.

Microelectronic mechanical system and methods

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF 2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

Dry etching of polydimethylsiloxane for microfluidic systems

Abstract: A fluorine-based reactive ion etch (RIE) process has been developed to anisotropically dry etch the silicone elastomer polydimethylsiloxane (PDMS). This technique complements the standard molding procedure that makes use of forms made of thick SU-8 photoresist to produce features in the PDMS. Total gas pressure and the ratio of O2 to CF4 were varied to optimize etch rate. The RIE recipe developed in this study uses a 1:3 mixture of O2 to CF4 gas resulting in a highly directional and stable etch rate of approximately 20 μm per hour. Selective dry etching can be performed through a photolithographically patterned metal etch mask providing greater precision and alignment with preexisting molded features. The dry etch process is presented in this article along with a brief comparison to recently reported wet etch approaches.

Fabrication method of semiconductor integrated circuit device

Abstract: The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, or the silicon carbide film or the organic insulating film exposed to the side walls of the interconnection grooves are side-etched When a lamination film made of a silicon oxide film, an organic insulating film, a silicon oxide film, an organic insulating film and a silicon carbide film is dry-etched to form interconnection grooves over Cu interconnections, a mixed gas of SF 6 and NH 3 is used as an etching gas for the silicon carbide film to work side walls of the interconnection grooves perpendicularly and further suppress defects that a deposit or a reactant adheres to the surface of the Cu interconnections exposed to the bottom of the interconnection grooves

Manufacturing of high aspect-ratio p-n junctions using vapor phase doping for application in multi-Resurf devices

Abstract: A new technique to manufacture vertical Resurf devices is presented, in which the alternating p-n junctions in the drift region are formed by a combination of trench etching and vapor phase doping (VPD). Scanning capacitance microscopy (SCM) was performed to investigate these deep p-n junctions, showing a uniform doping profile along the full depth of the devices. Electrical measurements on such Resurf diodes display an increase in breakdown voltage from 30 V to 145 V for a device with a 10 /spl mu/m deep drift region doped at 3.5/spl times/10/sup 16/ cm/sup -3/. Such a concept leads to prediction of a specific on-resistance well below the silicon limit for an equivalent MOSFET.

Method of forming self-aligned contact structure with locally etched gate conductive layer

Abstract: A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

Ionized PVD with sequential deposition and etching

Abstract: An iPVD apparatus (20) is programmed to deposit material (10) into high aspect ratio submicron features (11) on semiconductor substrates (21) by cycling between deposition and etch modes within a vacuum chamber (30). The modes operate at different power and pressure parameters. Pressure of more than 50 mTorr, for example, is used for sputtering material from a target while pressure of less than a few mTorr, for example, is used to etch. Bias power on the substrate is an order of magnitude higher for etching, producing several hundred volt bias for etching, but only a few tens of volts for deposition. The alternating etching modes remove deposited material that overhangs edges of features on the substrate, removes some of the deposited material from the bottoms (15) of the features, and resputters the removed deposited material onto sidewalls (16) of the features. The substrate (21) is cooled during deposition and etching, and particularly during etching to substantially below 0°C. RF energy is coupled into the chamber (30) to form a high density plasma, with substantially higher RF power coupled during deposition than during etching. The substrate (21) is moved closer to the plasma source during etching than during deposition.

Plasma etching of silicon carbide

Abstract: A process for plasma etching silicon carbide with selectivity to an overlying and/or underlying dielectric layer of material. The dielectric material can comprise silicon dioxide, silicon oxynitride, silicon nitride or various low-k dielectric materials including organic low-k materials. The etching gas includes a chlorine containing gas such as Cl2, an oxygen containing gas such as O2, and a carrier gas such as Ar. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrate.

Method of manufacturing semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, capable of improving the embedding ability of a polysilicon layer in an embedded strapped part. SOLUTION: A collar oxide film 15a is left only on the sidewall of a trench 13, and then a nitride film 16a is formed over the whole surface. Next, the nitride film 16a is removed under first etching conditions, to leave the nitride film 16a only on the sidewall of the collar oxide film 15a. Then, the collar oxide film 15a is removed under second etching conditions, to expose a part of the surface of the semiconductor substrate 11 in the trench 13, to thereby form an opening 17 of an embedded strap. Then, the whole nitride film 16a is removed, and then a polysilicon layer is formed over the whole surface to embed the trench 13 and the opening 17 in a single step.

Process integration of self-assembled polymer templates into silicon nanofabrication

Abstract: Self-assembled diblock copolymer thin films are used as sacrificial layers for the transfer of dense nanoscale patterns into more robust materials. We detail the processes used to achieve highly uniform nanoporous dielectric films, high-aspect-ratio nanotextured silicon, silicon nitride dot arrays, silicon pillar arrays, and silicon tip arrays. All techniques are compatible with standard semiconductor fabrication processes. We also discuss the possible applications of each resulting nanometer-scale structure, including high surface area substrates for capacitors and biochips, quantum dot arrays for nonvolatile memories, and silicon pillar arrays for vertical transistors or field-emission displays.

Semiconductor transistor having a backfilled channel material

Abstract: A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.

In-plane control of morphology and tunable photoluminescence in porous silicon produced by metal-assisted electroless chemical etching

Abstract: Photoluminescent porous silicon (PSi) was produced by Pt-assisted electroless etching of p−-Si (100) in a 1:2:1 solution of HF, H2O2, and methanol. The peak emission wavelength of the PSi could be tuned in the range 500 nm⩽λ⩽600 nm simply by changing the time of etching. The luminescence is sufficiently intense at all wavelengths to be visible by eye. Furthermore, by patterning the metal areas on the surface prior to etching, the luminescence can be controlled spatially. To investigate the relationship among processing variables — principally etch time and spatial proximity to Pt — and morphology, scanning electron microscopy (SEM), true color fluorescence microscopy, and spatially resolved phonon line shape studies were undertaken. SEM images show nanocrystalline features in the region where the luminescence originates, a region which shifts spatially as a function of etch time, as indicated by fluorescence microscopy. Raman scattering measurements of the shift and broadening of the longitudinal optical ...

Microstructure, composition, and etching topography of dental ceramics.

Abstract: Purpose Topographic analysis of etched ceramics provides qualitative surface structure information that affects micromechanical retention mechanisms. This study tested the hypothesis that the etching mechanism changes according to the type of etchant and the ceramic microstructure and composition. Materials and methods Quantitative and qualitative analyses of 15 dental ceramics were performed using scanning electron microscopy, back-scattered imaging, X-ray diffraction, optical profilometry, and wavelength dispersive spectroscopy based on Phi-Rho-Z correction. All ceramic specimens were polished to 1 micron with diamond compound, and the following etchants and etching times were used: ammonium bifluoride (ABF) for 1 minute, 9.6% hydrofluoric acid (HF) for 2 minutes, and 4% acidulated phosphate fluoride (APF) for 2 minutes. Results HF produced an irregular etching pattern in which pores were the characteristic topographic feature. ABF-etched ceramic surfaces showed mostly grooves, and APF etchant caused a buildup of surface precipitate. Core ceramics showed less topographic change after etching because of their high alumina content and low chemical reactivity. Conclusion The observations suggest that the etching mechanism is different for the three etchants, with HF producing the most prominent etching pattern on all dental ceramics examined.

Etch process for etching microstructures

Abstract: A two-step method of releasing microelectromechanical devices from a substrate is disclosed. The first step comprises isotropically etching a silicon oxide layer sandwiched between two silicon-containing layers with a gaseous hydrogen fluoride-water mixture, the overlying silicon layer to be separated from the underlying silicon layer or substrate for a time sufficient to form an opening but not to release the overlying layer, and the second step comprises adding a drying agent to substitute for moisture remaining in the opening and to dissolve away any residues in the opening that can cause stiction.

Method of etching tungsten or tungsten nitride in semiconductor structures

Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing a rapid etch rate. In particular, the method employs the use of a plasma source gas where the chemically functional etchant species are generated from a combination of sulfur hexafluoride (SF 6 ) and nitrogen (N 2 ), where the sulfur hexafluoride and nitrogen are provided in a volumetric flow rate ratio within the range of about 1:2.5 to about 6:1.

Self-aligned contact etch with high sensitivity to nitride shoulder

Abstract: A method and apparatus are provided for etching semiconductor and dielectric substrates through the use of plasmas based on mixtures of a first gas having the formula CaFb, and a second gas having the formula CxHyFz, wherein a/b ≥ 2/3, and wherein x/z ≥ 1/2. The mixtures may be used in low or medium density plasmas sustained in a magnetically enhanced reactive ion chamber to provide a process that exhibits excellent corner layer selectivity, photo resist selectivity, under layer selectivity, and profile and bottom CD control. The percentages of the first and second gas may be varied during etching to provide a plasma that etches undoped oxide films or to provide an etch stop on such films.

Method for pitch reduction

Abstract: A method for pitch reduction is disclosed. The method can form a pattern with a pitch ⅓ the original pitch formed by available photolithography technologies by only using one photo mask or one pattern transfer process, self-aligned etching back processes, and conventional deposition processes. By choosing appropriate layers to be deposited and etched, the pattern can be an etching mask or it can be a device structure itself.