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Showing papers on "Fabrication published in 1986"


Patent
10 Mar 1986
TL;DR: Submicron lateral device structures, such as bipolar transistors, Schottky barrier diodes and resistors, are made using selfaligned fabrication techniques and conventional photolithography.
Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of as layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

106 citations


Book
01 Sep 1986
TL;DR: In this paper, a model for the Oscillatory Structure in the J(V) Characteristics of GaAs/(AlGa)As Tunneling Structures is presented, as well as the effect of subband structure on the Thermopower of a Quasi-1D Wire.
Abstract: I Physics and Engineering of Microfabrication.- High Resolution Lithography (Some Comments on Limits and Future Possibilities).- Submicron Lithography Tools.- Electron Beam Nanolithography.- The Spin Coating Process Mechanism.- Resists Patterning.- Dry Etching: Concepts, Methods and Applications.- Overlayers.- Self-Aligned Growth of Microstructures.- Laser-Induced Growth of Microstructures.- Structural Characterization of Superlattices by X-Ray Diffraction.- Recently Developed TEM Approaches for the Characterisation of Semiconductor Heterostructures and Interfaces.- Fabrication of Small Structures of Semiconductors and Metals.- Atomically Controlled Growth in 2, 1 and OD, and Applications.- Microstructure of Organic Mono- and Multilayers.- II Physics of Microstructures.- Fundamentals of Low Dimensional Physics.- Electron States in Semiconductor Microstructures.- Quantum Transport Theory for Small-Geometry Structures.- Noise in Microstructures.- Transport Physics of Multicontact Si MOS Nanostructures.- 1D Structures - Field Confinement Approach.- Excitons in GaAs Quantum Wells: Interface Disorder and Mobility.- Nonlinear Optics and Electro-Optics of Quantum Wells.- Quantum Interference Effects in Small Systems: Normal and Superconducting Networks.- 2D Localisation and Interaction Effects in Semiconductor Structures.- Optical Nonlinearities in Small Particles and Composite Materials.- Tunnel Currents and Electron Tunnelling Times in Semiconductor Heterostructure Barriers inPresenceanMagnetic Field.- III Perspectives in Microfabrication Applications.- Scaling Limits of Silicon VLSI Technology.- Three Part Series on Heterojunction Transistors.- CAD: Overview and Perspectives.- Silicon-on-Insulator Technology Leading Towards Three-Dimensional Integration of Microelectronics.- The Metal Base Transistors.- An Integrated Microfabrication System for Low-Dimensionality Structures and Devices.- Fabrication of Gate Array Interconnect Structures Using Direct-Write Deposition Processes.- Electronic Neural Computing.- IV Poster Session, Abstracts.- Fabrication of Submicron Structures Combining E-Beam and Deep-UV Exposure.- Fabrication of Short-Gate GaAs MESFETs by Electron Beam Lithography.- 2D Josephson Junction Networks.- Electric Field Heating of Supported and Free-Standing AuPd Fine Wires.- High-Frequency Limits of Quantum Noise Detectors Based on Superconducting Tunnel Junction Mixers.- Photoresponse and Transport Properties of a 'Quasi' Graded Gap Superlattice P-I-N Diode.- Disorder and Two-Dimensional Electronic Sub-Bands.- A Model for the Oscillatory Structure in the J(V) Characteristics of GaAs/(AlGa)As Tunneling Structures.- A Minute Metallic Sphere Close to Flat Metal Surface System: A Scanning Tunneling Microscope Problem.- A Calculation of the Effect of Subband Structure on the Thermopower of a Quasi-1D Wire.- The Effect of Electron-Electron Scattering on the Distribution Function in Semiconductors.- Index of Contributors.

97 citations


PatentDOI
TL;DR: In this article, an improved spin-on technology is presented for the deposition of dielectric films in the fabrication of integrated circuits (ICs), where a solution of polymers derived from cyclosilazanes is employed to deposit dielectrics films on semiconductor substrates by the spin on technology.

35 citations


Proceedings ArticleDOI
01 Jan 1986
TL;DR: In this paper, the authors address two fundamental issues: a significant miniaturation of micromechanical devices and IC-compatible construction of different types of micro-electronic components, and the justification for this research direction is found in a strong interest in sensor systems or multiple transducers and data extraction circuitry on a single chip.
Abstract: Research ef for ts on micromechanical sensors a t the Wisconsin Center for Applied Microelectronics have addressed two fundamental issues: a significant miniaturation of mech nical devices and IC-compatible construction te hniques. The justif ication for this research direction is found in a strong interest in sensor systems or multiple transducers and data extraction circuitry on a single chip.

35 citations



Journal ArticleDOI
TL;DR: In this article, the authors focus mainly on the recent development of mass production by VAD process and highlight the recent R&D effort in VAD optical fibers can be summarized as: improving transmission characteristics, volume production enhancement, fluorine doping techniques, 4) 1.55 pm zero-dispersion wavelength, long length/high strength manufacture, and 6) high NA fabrication.
Abstract: ESEARCH AND DEVELOPMENT of the Vapor Phase Axial Deposition (VAD) process for commercialization was continued after invention in 1977 to manufacture optical fibers of low loss and wide bandwidth. Around 1981, optical fibers by the VAD process began to be manufactured in volume production [1]-[8]. The large,number of reports were published regarding research and development during this time are well summarized in [l] , [2]. Graded-index (GI) fiber cables were first used in city trunk networks beginning in 1981. Single-mode (SM) fiber cables were commercially introduced in the nationwide trunk networks beginning in 1983. A large portion of these cables contained GI and SM fibers manufactured by the VAD process [8], 191. Typical characteristics of factory-produced VAD fibers at present are summarized as Table I [2], [4], [6]-[8]. The recent R&D effort in VAD optical fibers can be summarized as: 1) improving transmission characteristics, 2) volume production enhancement, 3) fluorine doping techniques, 4) 1.55 pm zero-dispersion wavelength, 5) long length/high strength manufacture, and 6) high NA fabrication. This paper focuses mainly on the recent development of mass production by VAD process.

29 citations


Journal ArticleDOI
TL;DR: In this article, a fabrication method for single shell targets and an extension of this technique also enables us to fabricate double shell targets is presented. But this method is not suitable for the fabrication of multilayer targets and low density, thick polymer layer-coated targets.
Abstract: Deuterated polystyrene as a target material offers several advantages over other polymers because of the following: (1) it is chemically and physically stable at ordinary conditions, (2) it can be easily formed into spherical shells, and (3) it has a very high fraction of D2/H2 (above ∼99%). As in our previous studies, the fabrication method was basically a utilization of the emulsion technique. This method is well suited to mass‐producing the polymer targets without microprocessing techniques. We have developed a fabrication method for single shell targets and an extension of this technique also enables us to fabricate double shell targets. This new method is faster and less labor intensive than previous techniques. The development of ICF experiments requires multilayer structure targets; we have developed, moreover, a new fabrication technique called the multicoating method. The polymer coating can be fabricated by the application of an emulsion technique. On the other hand, with metal coating, a nonelectroplating method was used, and nickel was employed as the coating metal. The thickness of the polymer coating layer can be controlled with the rotational speed of a stirrer in the emulsion. In the case of nickel coating, it is achieved by controlling the plating bath temperature and immersion time during the plating process. The experiment resulted in the development of a new technique for the fabrication of multilayer targets and low density, thick polymer‐layer‐coated targets.

27 citations


Patent
25 Jul 1986
TL;DR: A self-alignment process for the fabrication of an array formed from a plurality of micron-scale solid state circuit elements operatively disposed upon a large area substrate was proposed in this article.
Abstract: A self-alignment process for the fabrication of an array formed from a plurality of micron-scale solid state circuit elements operatively disposed upon a large area substrate. By the instant process electrical contact may be established with the upper electrode of the micron-scale solid state circuit elements without the necessity of masking.

25 citations


Journal ArticleDOI
TL;DR: In this article, the electrical properies of wires made in this way have been investigated and other applications of these techniques are discussed, including electron beam lithography and dry etching.

24 citations


Book ChapterDOI
01 Jan 1986

21 citations


Patent
31 Mar 1986
TL;DR: In this paper, a method of fabrication of non-linear control elements for a flat display screen of the liquid crystal type is described, in which successive layers of n30 doped amorphous semiconductor, of undoped ammorphous semiconduct and of metal are deposited on a substrate, whereupon the control elements are formed by masking and etching.
Abstract: In a method of fabrication of non-linear control elements for a flat display screen of the liquid crystal type, successive layers of n30 doped amorphous semiconductor, of undoped amorphous semiconductor and of metal are deposited on a substrate, whereupon the control elements are formed by masking and etching. The flanks of the control elements are then isolated, whereupon the electrodes and control leads are formed by deposition and etching.

Journal ArticleDOI
TL;DR: In this article, the fabrication and evaluation of D-fibres, whose optical properties are compatible with standard single-mode fiber designs, is reported, and the high tolerances achieved in the process of drawing a tapered preform are shown to be necessary for predicting the transverse coupling behaviour of the fibres.
Abstract: The fabrication and evaluation of D-fibres, whose optical properties are compatible with standard single-mode fibre designs, is reported. The high tolerances achieved in the process of drawing a tapered preform are shown to be necessary for predicting the transverse coupling behaviour of the fibres.

Journal Article
TL;DR: In this paper, the authors identified the likely cause of the 20% (AM 1) efficiency barrier in the highest efficiency silicon solar cells reported to date, and proposed several novel emitter designs to reduce recombination losses.
Abstract: Abstract Based recombination at residual defect and impurity recombination centers is identified to be the likely cause of the 20% (AM 1) efficiency barrier in the highest efficiency silicon solar cells reported to date. To reach the 20% (AM 1) efficiency, base recombination must be further reduced by either stress-free and clean fabrication techniques on high lifetime crystals or novel base structure design, such as the graded thin-base back-surface-field structure proposed and analyzed by Sah and Lindholm. To break the 20% barrier, residual base recombination losses must be eliminated and emitter recombination must be reduced. Several novel emitter designs to reduce recombination losses have been proposed and one demonstrated. These involve the reduction of emitter interface recombination losses at the non-contact surface by high quality thermal oxide and at the metal-contact/silicon-emitter interface by either a thin tunneling oxide, as demonstrated by Green, or by a polysilicon barrier layer between the metal conductor and the silicon emitter surface. An efficiency of 23.8% (AM 1) has been estimated using Neugroschel's data on emitter interface recombination velocity and dark current density of polysilicon barrier layers. Novel floating emitter or non-contact emitter solar cell transistor structures have also been proposed by Sah and Cheng to reduce emitter recombination loss for >20% efficient silicon solar cells.

Journal ArticleDOI
TL;DR: In this article, limited reaction processing (LRP) has been used to achieve the in-situ growth of epitaxial silicon-oxide-doped polysilicon layers.
Abstract: Limited reaction processing (LRP) has been used to achieve the in-situ growth of epitaxial silicon-oxide-doped polysilicon layers. The in-situ growth of these multiple layers was combined with the selective epitaxial growth technique to create structures for MOSFET fabrication. The results of n- and p-channel transistor fabrication utilizing these structures are presented.

Journal ArticleDOI
TL;DR: In this paper, the use of a pulsed UV excimer laser based process for the incorporation of dopant impurities into Si is described, which can result in high concentration shallow box like profiles suitable for submicron VLSI device fabrication.
Abstract: The use of a pulsed UV excimer laser based process for the incorporation of dopant impurities into Si is described. The process can result in high concentration shallow box like profiles suitable for submicron VLSI device fabrication. The process consists of exposure of the clean silicon surface to a doping gas (B2H6, AsH3, PH3) then driving the adsorbed monolayers of dopant into the Si by a melt-regrowth process initiated by a pulsed XeCl excimer laser. Modeling of the process allows prediction of the resulting doping profiles and electrical properties of the doped layers. Excellent crystal quality of the doped layers is found even without a post-doping anneal. Also, recent results indicate that post doping annealing may not be needed for improvement of the electrical characteristics of the doped layers provided certain conditions are met. Detailed descriptions of the process, results, modeling and device fabrication are presented.

Journal ArticleDOI
TL;DR: In this article, a multimode fiber having no P 2 O 5 in the core has been demonstrated which also exhibits uniform forward and cutback bandwidth-length dependence and improved resistance to the effects of hydrogen.
Abstract: Improvements in optical fiber fabrication made over the last two years using the outside vapor deposition (OVD) process are reported. Advances have been made in the areas of optical and mechanical performance for existing products, dopant changes, and single-mode fiber designs. A multimode fiber having no P 2 O 5 in the core has been demonstrated which also exhibits uniform forward and cutback bandwidth-length dependence and improved resistance to the effects of hydrogen. Data is also presented on a dispersion-shifted single-mode fiber made using the segmented core approach which has recently been put into production.

Journal ArticleDOI
TL;DR: In this paper, the authors report the fabrication of very low threshold buried heterostructure lasers by a two-step MOCVD technique and show very high yield of fabrication, very high uniformity of the initial characteristics, good reproducibility, and low degradation rate during the aging test.
Abstract: We report the fabrication of very low threshold buried heterostructure lasers by a two-step MOCVD technique. We show very high yield of fabrication, very high uniformity of the initial characteristics, good reproducibility, and low degradation rate during the aging test.

Patent
13 Feb 1986
TL;DR: In this article, a high precision mirror using a discontinuous metal matrix mposite is described, which is machined to form a mirror substrate which is then coated and the coating so obtained is converted into the mirror surface.
Abstract: Fabrication of a high precision mirror using a discontinuous metal matrix mposite is described. A metal matrix composite (MMC) is obtained by using one of the three methods described herein or any other method. The MMC material so obtained is machined to form a mirror substrate which is then coated and the coating so obtained is converted into the mirror surface. The mirror so obtained has better characteristics over the conventional high precision beryllium mirrors used for this purpose and is fabricated out of a nontoxic material which is cheaper and more easily available than the beryllium metal.

Journal ArticleDOI
TL;DR: In this article, the electron windows of BN or SiC are used as electron windows for the fabrication of x-ray mask substrates with high yield strength, low mass density, and low atomic number.
Abstract: The refractory thin films of BN or SiC typically used in the fabrication of x‐ray mask substrates are characterized by a very high yield strength, low mass density, and low atomic number. The deposition of these films by standard semiconductor techniques, low pressure chemical vapor deposition (LPCVD), coupled with orientation dependent etching of the substrate, allows the straightforward fabrication of defect‐free, vacuum‐tight membranes capable of supporting atmospheric pressure. Used as electron windows, these films are also distinguished by their high transmission of moderate energy electrons (typically 87% at 25 keV). The ease of deflection and modulation of electrons at these energies, and their availability in air or other media via one of these windows mounted on a cathode ray tube (CRT), allow a number of possible applications. Two such applications are reported here.


Journal ArticleDOI
TL;DR: In this article, an integrated vapor sensor incorporating a resonant poly-Si microbridge and on-chip NMOS circuitry is described, which has a Young's modulus of 4×1010Nm−2, substantially lower than crystalline silicon.
Abstract: Polycrystalline silicon (poly-Si) micromechanical structures can be made by selectively etching an underlying sacrificial oxide layer. Advantages of this micromachining technique are its simplicity and compatibility with conventional integrated-circuit processing. Compressive internal stress in poly-Si films constrains the dimensions of microstructures; fortunately, it can be reduced through annealing. Fabrication of an integrated vapor sensor incorporating a resonant poly-Si microbridge and on-chip NMOS circuitry is described. Frequency response measurements imply that poly-Si films have a Young's modulus of 4×1010Nm−2, substantially lower than crystalline silicon. A potential application of poly-Si micromachining is fabrication of an integrated pressure transducer; evaluation of this device identifies areas for further research.


Journal ArticleDOI
TL;DR: In this article, the formation of the oxide barrier was studied by in situ ellipsometry, and SiO was developed as the insulation layer with less defect density than conventional SiO. The characteristics of each element in the circuits were evaluated for test vehicles.
Abstract: Fabrication technology for lead‐alloy Josephson devices was evaluated from the viewpoint of application to large‐scale integrated circuits. Metal and insulating layers used in the circuits were evaluated, and optimization of techniques for deposition or formation of these layers was investigated. Metallization of the Pb‐In‐Au base electrode and the Pb‐Bi counterelectrode was studied in terms of optimizing the deposited films, to improve the reliability of junction electrodes. The formation of the oxide barrier was studied by in situ ellipsometry. SiOx deposited in oxygen was developed as the insulation layer with less defect density than conventional SiO. A liftoff technique using toluene soaking was developed, and patterns with a minimum line width of 2 μm were consistently reproduced. The characteristics of each element in the circuits were evaluated for test vehicles. For the junction, the following items were evaluated: controllability of the critical current Ic, junction quality, Ic uniformity, junct...

Journal ArticleDOI
TL;DR: In this article, a single-level-resist process was used to fabricate GaAs MESFETs with gate lengths as short as 28 nm on MBE grown epi-layers.

Patent
07 Mar 1986
TL;DR: In this paper, novel opto-isolator devices and processes for fabricating same wherein suitable semiconductive substrates, such as galium arsenide wafers, are treated with conductivity type determining impurities in such a manner as to form radiation emitters, radiation detectors and interconnecting waveguides therein.
Abstract: Disclosed are novel opto-isolator devices and processes for fabricating same wherein suitable semiconductive substrates, such as galium arsenide wafers, are treated with conductivity type determining impurities in such a manner as to form radiation emitters, radiation detectors and interconnecting waveguides therein. These operative regions which form a monolithic opto-isolator have the necessary electro-optical characteristics for generating and coupling radiation from the emitter and through the waveguide coupler to the detector; and all of these regions may be integrally fabricated in a monolithic batch fabrication process. Such process may use, for example, particle implantation and masking steps, thereby ensuring high yield and low cost device fabrication.

Journal ArticleDOI
TL;DR: The case for the interdisciplinary fabrication of small structures is made using molecular and atomic forces in a building-up approach as a complimentary alternative to the semiconductor carving-out mode.

Journal ArticleDOI
TL;DR: In this article, the porosity distribution depends mostly on the density of the sintered products: up to 77% T.D. all pores are open and above 89-90%T.D usually closed.

Proceedings ArticleDOI
01 Dec 1986
TL;DR: In this article, the elastic coefficients of carbon-carbon composites were measured at four steps during the fabrication process and an ultrasonic materials characterization testbed was used to show that the carbonization-induced porosity drastically affects the anisotropy factor 2C66/Cz z-C1 2.
Abstract: The elastic coefficients of carbon-carbon composites were measured at four steps during the fabrication process. An ultrasonic materials characterization testbed was used to show that the carbonization-induced porosity drastically affects the anisotropy factor 2C66/Cz z-C1 2. These and other results suggest that the use of ultrasonic waves (by noncontact methods such as photoacoustics) could provide a me$ningful technique for monitoring the fabrication process and thereby allow optimization of the control parameters and ultimately the quality and processing speed of the final product.

Journal ArticleDOI
TL;DR: In this article, a new fabrication technique for integrated-optical tapers with controllable profiles on a GaAs substrate by selective liquid-phase epitaxy is proposed based on two-dimensional numerical results, and preliminary experimental results are given
Abstract: A new fabrication technique for integrated-optical tapers with controllable profiles on a GaAs substrate by selective liquid-phase epitaxy is proposed based on two-dimensional numerical results, and preliminary experimental results are given This technique takes advantage of the dependence of the epitaxial layer thickness on the window width

Journal ArticleDOI
TL;DR: In this article, a solution proximity annealing technique was used to capless anneal ion-implanted GaAs, using an arsenic-saturated solution of Sn and Ga in close proximity to the wafer, to the fabrication of GaAs integrated circuits.
Abstract: A technique for capless annealing of ion-implanted GaAs, using an arsenic-saturated solution of Sn and Ga in close proximity to the wafer, has been applied to the fabrication of GaAs integrated circuits. The IC processing technology utilizes a self-aligned T-shaped refractory gate approach for the fabrication of both enhancement- and depletion-mode MESFET's. Using the solution proximity annealing technique, excellent threshold voltage uniformities (standard deviation = 26 mV) have been obtained for enhancement-mode devices using commercial substrates. This process technology has resulted in the fabrication of divide-by-16 circuits in both SDFL and DCFL logic implementations, as well as enhancement/depletion (E/D) ring oscillators (L g = 2 µm) with propagation delays as low as 45 ps/gate and concomitant power consumptions of 2 mW/gate. This technique can also be applied, by suitable choice of the solution constituents, to capless annealing of other III-V semiconductors such as InP and GaInAs.