Fabrication

About: Fabrication is a research topic. Over the lifetime, 20475 publications have been published within this topic receiving 235676 citations.

Fabrication of GaInP/GaAs//Si Solar Cells by Surface Activated Direct Wafer Bonding

Abstract: GaInP/GaAs//Si solar cells with three active p-n junctions were fabricated by surface activated direct wafer bonding between GaAs and Si. The direct wafer bond is performed at room temperature and leads to a conductive and transparent interface. This allows the fabrication of high-efficiency monolithic tandem solar cells with active junctions in both Si and the III-V materials. This technology overcomes earlier challenges of III-V and Si integration caused by the large difference in lattice constant and thermal expansion. Transmission electron microscopy revealed a 5-nm thin amorphous interface layer formed by the argon fast atom beam treatment before bonding. No further defects or voids are detected in the photoactive layers. First triple-junction solar cell devices on Si reached an efficiency of 23.6% under concentrated illumination.

Electrochemical fabrication of highly ordered semiconductor and metallic nanowire arrays

Abstract: In this article, we report the fabrication of highly ordered TiO2 nanowire arrays by anodic oxidative hydrolysis of TiCl3 within a hexagonal close-packed nanochannel alumina (NCA). The single-crystalline anatase TiO2 nanowires with diameters about 15 nm and lengths about 6 μm are obtained after annealing at 500 °C. Finally, the fabrication and characterization of highly ordered Au and Ni nanowire arrays with selectable diameters are also reported.

High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis

Abstract: We demonstrate high yield fabrication of field effect transistors (FET) using chemically reduced graphene oxide (RGO) sheets suspended in water assembled via dielectrophoresis. The two terminal resistances of the devices were improved by an order of magnitude upon mild annealing at 200 0C in Ar/H2 environment for 1 hour. With the application of a backgate voltage, all of the devices showed FET behavior with maximum hole and electron mobilities of 4.0 and 1.5 cm2/Vs respectively. This study shows promise for scaled up fabrication of graphene based nanoelectronic devices.

Low-temperature polysilicon thin film transistors on polyimide substrates for electronics on plastic

Abstract: In this work we show a new low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) fabrication process on polyimide (PI) layers. The PI is spun on Si-wafer used as rigid carrier, thus overcoming difficulties in handling flexible freestanding plastic substrates, eliminating the problem of plastic shrinkage with high temperature processing and allowing the use of standard semiconductor equipment. LTPS TFTs are fabricated according to a conventional non self-aligned process, with source/drain contacts formed by deposition of a highly doped Si-layer and patterned by a selective wet-etching. Laser annealing is performed providing simultaneous dopant activation and crystallization of the active layer. The maximum process temperature is kept below 350 °C. After LTPS TFTs fabrication, the PI layer is mechanically released from the rigid carrier, which can be re-used for a new fabrication process. The devices exhibit good electrical characteristics with field effect mobility up to 50 cm 2 /V s. Analysis of electrical stability and characteristics in presence of mechanical stress is also shown.