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Showing papers on "Fast packet switching published in 1986"


Journal ArticleDOI
TL;DR: The performance of frequency-hop transmission in a packet communication network is analyzed and new measures of "local" performance are defined and evaluated for networks of this type, and new concepts that are important in the design of these networks are introduced.
Abstract: The performance of frequency-hop transmission in a packet communication network is analyzed. Satellite multiple-access broadcast channels for packet switching and terrestrial packet radio networks are the primary examples of the type of network considered. An analysis of the effects of multiple-access interference in frequency-hop radio networks is presented. New measures of "local" performance are defined and evaluated for networks of this type, and new concepts that are important in the design of these networks are introduced. In particular, error probabilities and local throughput are evaluated for a frequency-hop radio network which incorporates the standard slotted and unslotted ALOHA channel-access protocols, asynchronous frequency hopping, and Reed-Solomon error-control coding. The performance of frequency-hop multiple access with error-control coding is compared with the performance of conventional ALOHA random access using narrow-band radios.

162 citations


Patent
16 May 1986
TL;DR: In this article, a high performance packet switching network that can be used to provide voice data and video communication on a large scale is described, which makes it suitable for applications including commercial television distribution and conferencing.
Abstract: A high performance packet switching network that can be used to provide voice data and video communication on a large scale is disclosed. The packet switching network has a broadcast capability which makes it suitable for applications including commercial television distribution and conferencing. The basic switching capability of the network is provided by a switching module which is capable of producing a desired number of copies of a broadcast packet and routing the copied packets to desired destinations. A plurality of switching modules may be interconnected to form a packet switch. Interconnection circuitry is provided so that the number of interconnected switch modules may be varied with a minimum of recabling.

92 citations


Patent
Hiroshi Suzuki1
07 Oct 1986
TL;DR: In this article, a packet switched communications system is defined, where a plurality of switching nodes serve a pluralityof terminals through transmission links, and each of the terminals transmits a packet of data-link layer control protocol including a network-layer control protocol to an associated one of the switching nodes.
Abstract: Disclosed is a packet switched communications system wherein a plurality of switching nodes serves a plurality of terminals through transmission links. Each of the terminals transmits a packet of data-link layer control protocol including a network-layer control protocol to an associated one of the switching nodes. Each of the switching nodes is responsive to the network control protocol of the packet for routing it to one of the transmission links defined by the network layer control protocol of the packet. The switching node includes a plurality of line controllers associated respectively to the transmission links. Each line controller appends a physical address of the packet at the defined transmission link to the packet and updates its network-layer control protocol with a logical address of the packet at the defined transmission link and sends it to the line controller associated with the defined transmission link by way of a switching network.

80 citations


Patent
06 Dec 1986
TL;DR: In this article, the authors propose a packet switching architecture in which switching network nodes automatically determine nonblocking paths through a switching network in response to address information, and each node upon receipt of the acknowledge signal establishes the path through the itself.
Abstract: A packet switching architecture in which switching network nodes automatically determine nonblocking paths through a switching network in response to address information. The switching network comprises stages of broadcast and routing nodes. The broadcast nodes are responsive to the transmission of address information from an input port to create a plurality of paths through the switching network and to communicate on this plurality of paths the address information to the routing stages. Each of the routing switch nodes is responsive to receipt of address information to select one of the paths to an address-designated output port. The final path is established by the output port transmitting an acknowledge signal back through the switching network. Each node upon receipt of the acknowledge signal establishes the path through the itself.

64 citations


Patent
23 Jun 1986
TL;DR: In this paper, the authors proposed a packet switching protocol in which self-routing packets are communicated among stages of switching nodes via inter-stage links, where data of the packets is transmitted in one direction (210) and packet clocking signals are transmitted in the other direction (211).
Abstract: A communication method and packet switching network (101) in which self-routing packets are communicated among stages of switching nodes via inter-stage links (204-215) whereon data of the packets is transmitted in one direction (210) and the packet clocking signals are transmitted in the other direction (211). Upon having the capability to accept a packet from one of the interstage links, a switch node transmits the packet clock signals to the upstream stage connect to that link indicating the present capacity to accept a packet. Furthermore, each switch node after receiving the end of a packet from an upstream stage waits for a predefined duration of time before commencing the transmission of the packet clocking signals. That delay allows the transmitting switch node i the upstream stage to determine that the link and downstream node are functioning correctly since continued transmission of the packet clock signals indicates that the packet had not been received or that downstream node had incorrectly responded to receipt of the packet. If a malfunction is detected, an error indication is transmitted to the computer controlling the switching network.

63 citations


Patent
Fumio Miyao1
19 Mar 1986
TL;DR: In this article, the authors proposed a composite data transmission system where packet switching stations adapted to transmit data of the kind for which transfer delay and periodicity do not matter and operated to detect collisions between packets in the light of alterations in the DC voltage level of packet signals.
Abstract: A composite data transmission system wherein packet switching stations adapted to transmit data of the kind for which transfer delay and periodicity do not matter and operated to detect collisions between packets in the light of alterations in the DC voltage level of packet signals and circuit switching stations adapted to transmit data of the kind requiring periodic transmission are connected to one and the same transmission line, which composite data transmission system is characterized by causing DC voltage signals of a fixed magnitude to flow with prescribed periods through the transmission line thereby enabling the packet switching stations to recognize collisions and permitting the circuit switching stations to exchange communication during the existence of the packet switching stations' recognition of collisions and permitting the packet switching stations to exchange communication during the absence of the DC voltage signals' flow.

57 citations


Journal ArticleDOI
TL;DR: This methodology is useful for investigating cost/performance tradeoffs of various network capabilities and components, thus providing a means for identifying potential cost and performance bottlenecks for different packet technologies and to guide capability requirements for new technologies.
Abstract: This paper describes a packet network design and analysis (PANDA) model which captures the important features of different packet technologies. This model evolved from many iterations with technology developers and network planners over several years. The main contribution is a methodology for designing low-cost backbone packet networks with satisfactory performance which is both practical and useful. This methodology is useful for investigating cost/performance tradeoffs of various network capabilities and components, thus providing a means for identifying potential cost and performance bottlenecks for different packet technologies and to guide capability requirements for new technologies.

52 citations


Patent
Hideyuki Hirata1
11 Sep 1986
TL;DR: A packet switching system consists of a packet transmission controller, connected to a line group, for performing transmission control of a data packet, and a packet switching unit for receiving the data packet from the packet transmission Controller to perform switching processing as discussed by the authors.
Abstract: A packet switching system mainly consists of a packet transmission controller, connected to a line group, for performing transmission control of a data packet, and a packet switching unit for receiving the data packet from the packet transmission controller to perform switching processing. The packet switching unit includes a packet separator for separating the data packet into a header part and a data part, a packet header processor for updating the separated header part, a packet data buffer for storing the separated data part, and a packet combiner for combining the output from the packet data buffer and the output from the packet header processor and supplying a combined packet to the packet transmission controller.

52 citations


Patent
18 Jun 1986
TL;DR: In this paper, a packet switching network has a plurality of stages with each stage comprising a plurality-of-switch nodes, and the communicated packets can be of the single-destination, broadcast, or multipledestination types of packets.
Abstract: A communication method and packet switching network in which self-routing packets are communicated to a single-destination port of the switching network, a plurality of grouped destination ports or to two distinct destination ports after the modification by the switching network of the self-contained routing information within the packets. The packet switching network has a plurality of stages with each stage comprising a plurality of switch nodes, and the communicated packets can be of the single-destination, broadcast, or multiple-destination types of packets. The routing information within the packet comprises pairs of data bits with each pair associated with a stage of the switching network and with the value of the pair of bits determines the type of packet for the corresponding stage. Each switching node has two input and two output terminals, and a switch node in a particular stage is responsive to a single-destination packet received on an input terminal to communicate the packet to the output terminal designated by the value of the pair of bits for that stage. A switch node is responsive to a broadcast type packet to communicate the packet to both output terminals.

43 citations


Patent
Michio Suzuki1, Kano Takashi1, Tohru Hoshi1, Jiro Kashio1, Yasushi Takeuchi1 
15 Sep 1986
TL;DR: In this article, the center node estimates the state of delay of data for every relay line on the basis of information previously inputted, indicating the communication network configuration, and the reported state of data reported by each of the switching nodes.
Abstract: In a communication network, in which a plurality of switching nodes are connected with each other through a plurality of relay lines and one of the switching nodes acts as a center node for network routing, the center node estimates the state of delay of data for every relay line on the basis of information previously inputted, indicating the communication network configuration, and the state of delay of data reported by each of the switching nodes, and informs each of the switching nodes of said estimated state of delay of data. Each of the switching nodes determines and selects the relay line giving the shortest delay of data for every destination, to which it outputs data, on the basis of the state of delay at the relevant switching node itself and that received from the center node.

40 citations


Patent
07 Nov 1986
TL;DR: In this paper, a plurality of bits are stored in respective storage locations of the switching elements of a multistage interconnection network (MIN), where each storage location represents a particular time slot in a frame or a sequence of frames.
Abstract: This invention relates to a method of switching voice and data over a multistage interconnection network (MIN). More specifically, a plurality of bits are stored in respective storage locations of the switching elements of the MIN. Storage location of a switching element represents a particular time slot in a frame or a sequence of frames. Bits stored in each location represent specific conditions of the inputs and outputs of the switching elements and also indicate which inputs of the switching elements will be connected to which outputs of the switching elements. This storage of control information in the switching elements allows the switching network to rapidly and simultaneously change connections through the switching elements of the network.

Patent
29 Sep 1986
TL;DR: In this paper, a packet switching system for achieving high-speed packet switching on data lines having the X.25 protocol of the C.C.I.T. is presented.
Abstract: A packet switching system for achieving high-speed packet switching on data lines having the X.25 protocol of the C.C.I.T.T. It includes a plurality of data line apparatuses (DLC: 10, 11, and 1N), a call connection control information transfer bus commonly connected to the plurality of data line apparatuses (CB: 2), a specialized data transfer bus for data packets (DB: 4), a packet buffer state information transfer bus for transmitting and receiving call state information (SB: 6), and a call connection controlling processor connected to the call connection control information transfer bus (CP: 3). Each of the data line apparatuses has a receive packet storing circuit (DTRQ: 102) provided with a receive packet buffer of the first-in random out (FIRO) memory, and a transmit packet storing circuit (DTSQ: 105) provided with a transmit packet buffer of the FIRO memory.

Proceedings Article
01 Jan 1986
TL;DR: The authors discuss and propose a very-high-speed and high-capacity packet-switching (HPS) architecture for a future broadband ISDN (integrated-services digital network), which provides high flexibility for various communications services as well as high-speed capability.
Abstract: The authors discuss and propose a very-high-speed and high-capacity packet-switching (HPS) architecture for a future broadband ISDN (integrated-services digital network). The HPS network accommodates various communication services, such as voice, high-speed data, high-speed still picture, and video services. The proposed architecture has three significant principles: a high-speed oriented simple network protocol, separation of signaling and network control from data transfer, and hardware switching. These principles provide fast- and high-throughput transmission for data packets and reliable transmission and processing for call-control packets. The HPS protocol structure is addressed, which provides high flexibility for various communications services as well as high-speed capability. A 3-Gb/s capacity and building-block-structured packet-switching system architecture, using bus- and loop-type switch fabric, is also presented. >

Journal ArticleDOI
TL;DR: This paper is based on a study conducted by Bell Communications Research of outage data for various stored program control (SPC) switching systems (exchanges) in various Bell Operating Companies.
Abstract: This paper is based on a study conducted by Bell Communications Research of outage data for various stored program control (SPC) switching systems (exchanges) in various Bell Operating Companies. The outage causes were first classified into four basic categories. These basic causes were then subcategorized to further define the causes of failures.

Patent
29 Oct 1986
TL;DR: In this paper, a circuit for signalling the real-time end of a local area network packet as the packet is being pulled off a transmission medium and stored in memory is presented.
Abstract: Provided is a circuit for signalling the real-time end of a local area network packet as the packet is being pulled off a transmission medium and stored in memory. Storage of the packet is performed by a local area network coprocessor. The circuit monitors for the simultaneous occurrence of three conditions: the coprocessor is in a write-to-memory cycle; it is writing to the address of status word pertaining to a packet; and the most significant bit of the status word is being set. If all three conditions are true, the circuit asserts the real-time end-of-­packet signal.

Patent
16 Sep 1986
TL;DR: The Asynchronous Packet Manager (APM) as mentioned in this paper is an interface for transferring data in a first format between a data terminal equipment and a combination data and telephone switching system in a properietary packet format.
Abstract: The Asynchronous Packet Manager is the interface for transferring data in a first format between a data terminal equipment and a combination data and telephone switching system in a properietary packet format. A microprocessor accepts data from a universal asynchronous receiver transmitter and forwards the data to a mini packet receiver transmitter, when it is formatted into mini packets and converted to an alternate mark inversion signal and sent to the switching network.

Patent
08 Aug 1986
TL;DR: In this article, a throughput decision cycle is defined as a certain period reported by a throughput cycle switching report line 51, and the number of packets is counted by a transmission packet (throughput) counter 14 and the counted value is checked by throughput value comparator 16 whether this throughput value exceeds a maximum transmission throughput value stored in a throughput value holding device or not.
Abstract: PURPOSE: To realize the flow control which can cope with the overload condition of traffic, by controlling the transmission throughput by a packet terminal so that its own transmission throughput does not exceed a reported maximum throughput and abandoning excess packets or disconnecting a logical channel by an exchange if the packet terminal transmits packets with a throughput exceeding the reported value. CONSTITUTION: The number of packets is counted by a transmission packet (throughput) counter 14 in every throughput decision cycle which is a certain period reported by a throughput cycle switching report line 51, and the counted value is defined as the transmission throughput in the current cycle and is arranged with a network at the time of originating a call or the like, and it is checked by a throughput value comparator 16 whether this throughput value exceeds a maximum transmission throughput value stored in a throughput value holding device 15 or not. If it does not exceeds, a transmission permission report line 54 is set to the transmittable state and a packet transmission (throughput) controller 12 transmits packets from a transmission packet buffer 13. If it exceeds, the transmission permission report line 54 is set to the untransmittable state and the packet transmission (throughput) controller 12 stops the transmission. COPYRIGHT: (C)1988,JPO&Japio

Patent
16 Sep 1986
TL;DR: The Synchronous Packet Manager (SPM) as discussed by the authors is an interface for switching synchronous data between a data terminal equipment and a combination data and telephone switching system in a proprietary packet format.
Abstract: The Synchronous Packet Manager is the interface for switching synchronous data between a data terminal equipment and a combination data and telephone switching system in a proprietary packet format. A first microprocessor controlled circuit controls data to be received from the switching system or forwarded to it and communicates with a second microprocessor controlled circuit for controlling data to or from a terminal equipment via a common memory.

Journal ArticleDOI
TL;DR: When the channel is noisy, various properties of M/D/1 quasi-cut-through switching are investigated including actual traffic intensity and overall network delay including average transmission time of negative acknowledgment signal and queueing time for the retransmitted packet.
Abstract: Cut-through switching is advantageous in that it can reduce the transmission delay compared with the conventional message or packet switching. In this paper, when the channel is noisy, we investigate various properties of M/D/1 quasi-cut-through switching including actual traffic intensity and overall network delay. In the analysis of delay resulting from retransmission of erroneous packets, we have included the average transmission time of negative acknowledgment signal and queueing time for the retransmitted packet so that the overall network delay can be obtained accurately. In addition, we have obtained distributions of the number of nodes to be traversed and the number of nodes through which packets pass by cut. According to the analysis results, the performance of cut-through switching is superior to that of conventional packet switching in most practical ranges of parameter values.


Journal ArticleDOI
01 Aug 1986
TL;DR: The packet switch used in the DARPA Wideband Packet Satellite Network and the Butterfly#8482; Multiprocessor on which it is based is described.
Abstract: Multiprocessor computer systems have proven effective as high performance switching nodes in packet switched data communications networks. They are well suited to performing the required queuing, routing, and scheduling tasks, and can scale upward to provide higher system throughput when combined with software that exploits the parallelism provided by the hardware. This paper describes the packet switch used in the DARPA Wideband Packet Satellite Network and the Butterfly™ Multiprocessor on which it is based.


Patent
11 Jun 1986
TL;DR: In this article, an integrated service network (ISDN) is proposed to connect subscriber lines through a packet switching system to incoming or outgoing packet switching calls without passing them through a circuit switching system.
Abstract: An integrated service network ("ISDN") is structured to connect subscriber lines through a packet switching system to incoming or outgoing packet switching calls without passing them through a circuit switching system. This effectively uses the speech path of the circuit switching section instead of using it for packet switching calls. At the same time, the invention minimizes the influence of the introduction of the ISDN upon the software of the circuit switching section. The ISDN digital switching network applies to circuit switching calls which are switched at a local switch and to packet switching calls which are to be switched at a toll switch. The digital switching system separates calls into circuit switching calls which are transferred through B channels, packet switching calls which are transferred through B channels, and packet switching calls which are transferred through D channels in order to connect the circuit switching calls to a time division switch and the packet switching calls to a packet multiplexer. The packets are concentrated and multiplexed into separated packet switching calls. The circuit switching calls from the time division switch are multiplexed with the packet switching calls from the packed multiplexer and are placed in predetermined time slots in accordance with a band width designated corresponding to respective call traffic.

Journal ArticleDOI
TL;DR: An approach to the basic principles governing the definition of a fast packet transfer technique, called asynchronous time-division (ATD) transfer mode, has been investigated and a first implementation, the Prelude trial network, is presented.

Patent
18 Dec 1986
TL;DR: In this article, an improved combination of end-of-text (ETX) bytes along with checksums in each data packet was proposed to detect and recover from errors of transmissions in the form of a sequence of data packets.
Abstract: Automatic detection of and recovery from errors of transmissions in the form of a sequence of data packets is described as well as an improved combination of end-of-text (ETX) bytes along with checksums in each data packet to detect errors. The ETX character (12) is dynamically selected for each packet after the data comprising the packet has been assembled. This character is coded differently from the remaining character codes in its respective packet and is made the second byte thereof following the start-of-text byte (STX). The third byte (3) in each packet is made the complement of the preceding ETX byte, the latter of which is also made the last byte in the packet. Other bytes in each packet indude: one byte (4) indicating the location of the packet in a set in a given transmission sequence; a byte (7) distinguishing the packet's set from other transmission sequences; two bytes (5,6) indicative of the number of data bytes in the packet; one byte (8) operating as a control character indicating the functional nature of the packet; data bytes; and two checksum bytes (9,10+m) which precede the last ETX byte. Upon detection of an error in a packet, the transmitter is immediately notified and retransmission is carried out only from the erroneous packet rather than from the beginning of the entire sequence as in the prior art.

Patent
17 Jul 1986
TL;DR: In this paper, the authors propose to suppress an input to a packet switching set from a terminal, by adding a bit of information to represent a complicated state on a packet passing the packet-switching set, when the packet switch set falls in the complicated state.
Abstract: PURPOSE: To suppress an input to a packet switching set from a terminal, by adding a bit of information to represent a complicated state on a packet passing the packet switching set, when the packet switching set falls in the complicated state. CONSTITUTION: A complexity detecting part 1, and a suppression information adding part 2 are provided at a node, and a bit of suppression information is added on the packet in the reverse direction of the direction of communication in which the complicated state is generated at the node, then it is sent out. Since a logic link is not terminated, and a bit of information is added on a communication packet using the logic link, it is possible to send rapidly the bit of suppression information due to the complexity generated on the midvay of the logic link, to a terminating part. Also, by utilizing the fact that a transmission confirmation packet is transferred in the reverse direction of the direction of the communication along a communication logic link, the transmission confirmation packet of a junction line in the reverse direction corresponding to the junction line in the complicated, state can be captured. In this way, it is possible to inform the bit of suppression information due to the generation of the complexity automatically, to all of the equipments on a traffic generating terminal side performing the communication via a complicated junction line. COPYRIGHT: (C)1988,JPO&Japio

Patent
13 Aug 1986
TL;DR: In this article, the image information is transferred by dividing it into packet units, resending only a wrong packet, and restoring it at every packet, which can effectively utilize network resources such as a line, etc by maintaining the transfer efficiency.
Abstract: PURPOSE: To effectively utilize network resources such as a line, etc by maintaining the transfer efficiency, by transferring the image information by dividing it into packet units, resending only a wrong packet, as for the image information which has caused a packet error or a packet loss, and restoring it at every packet CONSTITUTION: One of image terminal equipments 11 which are connected to a switching network PS is used as an outgoing terminal 11, the other is used as an incoming terminal 11, and when image information is transferred between both terminals, each of information blocks is divided, reconstituted to plural packets 12, and the transfer is executed by a packet unit When a loss or an error of the packet 12 is detected by the incoming terminal 11, the incoming terminal 11 requests to the outgoing terminal 11 to resend the packet 12 which is lost or made an error and executes its restoration, and a transmittal confirmation between both the outgoing and incoming terminals is executed by using an exclusive block for resending the transmittal confirmation, after a transfer of plural packets 12 belonging to one information block is ended In such a way, a high transfer efficiency can be maintained, and network resources such as a line and an exchange, etc can be utilized effectively COPYRIGHT: (C)1988,JPO&Japio

Journal ArticleDOI
F. Melindo1, G. Valbonesi
TL;DR: An approach to ISDN suitable both for a pilot service, to be carried out in the near future in Italy, and for long-term developments with a high degree of penetration of ISDN setvices is presented.
Abstract: The paper presents an approach to ISDN suitable both for a pilot service, to be carried out in the near future in Italy, and for long-term developments with a high degree of penetration of ISDN setvices. Integration of ISDN services in the digital telephone exchange "UT" has taken place at all levels: system architecture, subscriber access structure, circuit connecting network, transmission links, call processing, and 0 & M functions. We also describe a new protocol that facilitates the dialog between exchange modules and between different exchanges for the data service. It is suitable for implementing packet transit switches with low complexity, high throughput, and low transit time. A special peripheral-handling processor handles the most repetitive functions of the protocols both in the local exchange and in other parts of the network, while the exchange central processor performs the ISDN call-handling functions; the same peripheral processors and the same module processor are used for both ISDN and telephone services. Finally, the paper shows how this architecture can evolve to include new wide-band services and new techniques to implement high-capacity fast packet switches.