Showing papers on "Fast packet switching published in 1989"

Bit-to-bit error dependence in slotted DS/SSMA packet systems with random signature sequences

Abstract: A technique is developed to find an accurate approximation to the probability of data bit error and the probability of packet success in a direct-sequence spread-spectrum multiple-access (DS/SSMA) packet radio system with random signature sequences. An improved Gaussian approximation to the probability of data bit error is performed. Packet performance is analyzed by using the theory of moment spaces to gain insight into the effect of bit-to-bit error dependence caused by interfering signal relative delays and phases which are assumed constant over the duration of a desired packet. Numerical results show that if no error control exists in the desired packet or if block error control is used when multiple-access interference is high, the error dependence increases the average probability of packet success beyond that predicted by models which use independent bit errors. However, when block error control is used and the multiple-access interference is low, the bit error dependencies cause a reduction in packet error performance. >

A survey of modern high-performance switching techniques

Abstract: A survey of high-performance switch fabric architectures which incorporate fast packet switching as their underlying switching technique to handle various traffic types is presented. A descriptive overview of the major activities in this rapidly evolving field of telecommunications is given. The switch fabrics are classified into the following categories: banyan and buffered banyan-based fabrics, sort-banyan-based fabrics fabrics with disjoint-path topology and output queuing, crossbar-based fabrics, time division fabrics with common packet memory, and fabrics with shared medium. >

An overview of lightwave packet networks

Abstract: The unique systems opportunities offered by, and the unique systems constraints imposed by, lightwave technology as it applies to the field of distributed packet networks are examined. Single-channel and star topology approaches are first considered. Terabit-capacity lightwave networks are discussed, covering both wavelength-division and time-division multiplexing. Multichannel multihop lightwave networks are then considered, and a particular implementation, the ShuffleNet, is described, and its performance, as well as some simple addressing and routing schemes, is discussed. >

Selective recovery of video packet loss using error concealment

Abstract: An efficient recovery method using error concealment is proposed for video packet loss in fast packet switching networks. In this method, the receiver detects the damaged picture area caused by packet loss from the structured picture data received, makes error concealments, notifies the transmitter, and continues decoding. The transmitter, having received the notice, calculates the affected picture area in the local decoded picture and continues encoding without using this affected area. In this selective recovery method, video signals are not stopped even if a long propagation delay exists, no additional information is transmitted to error recovery and conventional coding algorithms can be used. The proposed method is suitable for multipoint communication. Simulation results show the affected picture area is localized for a considerable time attesting to the method's effectiveness. >

Variable bit-rate coding of video signals for ATM networks

Abstract: Statistical characteristics of video signals for video packet coding, are clarified and a variable-bit-rate coding method for asynchronous transfer mode (ATM) networks is described that is capable of compensating for packet loss ATM capabilities are shown to be greatly affected by delay, delay jitter, and packet loss probability Packet loss has the greatest influence on picture quality Packets may be lost either due to random bit error in a cell header or to network control when traffic is congested A layered coding technique using discrete-cosine transform (DCT) coding is presented which is suitable for packet loss compensation The influence of packet loss on picture quality is discussed, and decoded pictures with packet loss are shown The proposed algorithm was verified by computer simulations >

Packet congestion control method and packet switching equipment

Abstract: A packet switching equipment housing therein a plurality of pairs of an input line and an output line is provided with a monitor circuit for monitoring a packet congestion state in the packet switching equipment for each output line. When a packet congestion is detected in association with either one of the output lines, a congestion indicator is added to a packet to be delivered to the output line so as to return the packet as a congestion notice packet to an equipment as the transmission source of the packet; furthermore, the input packet is relayed via the output line to the destination equipment.

Adaptive data link protocol

Abstract: A communication system provides high speed transmission of data over a link, such as a fiber optic link, between a first terminal and a second terminal. The architecture and protocol permits the use of dedicated hardware such as state machines constructed of programmable array logic units, to synchronize the transmission and reception of data packets and the retransmission of designated ones of these packets in the event of a faulty transmission. Packets to be transmitted and received are stored in an array of frames in sub-windows of a memory storage window in each of the termianls, the frame number being equal to the sequence number of the data packet. By embedding sequence and status bits in each packet within control words and bits appended to each packet, the state machine in each terminal can readily track the progress of each packet so as to request acknowledgement of error-free receipt, to send an acknowledgement, to request a retransmission of a packet designated by its serial number and to distinguish a retransmitted packet from an original packet transmitted with error.

Packet voice/data communication system having protocol independent repetitive packet suppression

Abstract: A data communication system includes a repetitive pattern packet suppression technique which suppresses transmission of entire packets in a data stream when a repeating pattern has been established in the previous packet and then is found to repeat throughout the following packets. An expansion part of the technique fills the resulting hole in the data stream with the last pattern from the previously received packet.

Dependence in packet queues

Abstract: The burstiness of the total arrival process has been previously characterized in packet network performance models by the dependence among successive interarrival times. It is shown that associated dependence among successive service times and between service times and interarrival times also can be important for packet queues involving variable packet lengths. These dependence effects are demonstrated analytically by considering a multiclass single-server queue with batch-Poisson arrival processes. For this model and more realistic models of packet queues, insight is gained from heavy-traffic limit theorems. This study indicates that all three kinds of dependence should be considered in the analysis and measurement of packet queues involving variables packet lengths. Specific measurements are proposed for real systems and simulations. This study also indicates how to predict expected packet delays under heavy loads. Finally, this study is important for understanding the limitations of procedures such as the queuing network analyzer (QNA) for approximately describing the performance of queuing networks using the techniques of aggregation and decomposition. >

A growable packet (ATM) switch architecture: design principles and applications

Abstract: The authors consider the generic problem of designing a large N*N(N>1000) high-performance, broadband packet (or asynchronous transfer mode) switch. They provide ways to construct arbitrarily large switches out of modest-size packet switches, without sacrificing overall delay/throughput performance. They propose and study a growable switch architecture based on three key principles: (a) a generalized knockout principle which exploits the statistical behavior of packet arrivals and thereby reduces the interconnect complexity; (b) output queuing, which yields the best possible delay/throughput performance; and (c) distributed intelligence in routing packets through the interconnect fabric. Other features include the guarantee of a first-in first-out packet sequence, broadcast and multicast capabilities, and compatibility with variable-length packets. In a broadband ISDN (integrated services digital network) example, the authors show a 2048*2048 switch configuration with building blocks of 42*16 packet switch modules and 128*128 interconnect modules. >

Multiwavelength networks and new approaches to packet switching

Abstract: The author shows how the bandwidth available through the use of multiwavelength optical-fiber technology can be used to achieve novel large-capacity switching systems to address anticipated switching bottlenecks. He does so by describing the features and network applications of a specific multiwavelength network, the Bellcore LAMBDANET packet switch. The discussion is then extended to a number of recent proposals for switching fabrics based on this new multiwavelength technology. The particular technologies he discusses are: the photonic knockout switch, a proposal similar to the concept of the LAMBDANET, but not requiring N receivers at each node; the FOX (fast optical cross-connect), an active wavelength routing approach; the ShuffleNet architecture; the HYPASS and BHYPASS switches; the coherent wavelength division lambda switch; and the Bellcore Star-Track multicast switch. >

Effect of speedup in nonblocking packet switch

Abstract: The nonblocking packet switch under consideration has N inputs and N outputs and operates L times as fast as the input and output trunks. The effect of speedup (L) on packet loss probability and average transmission delay in the case of an arbitrary number L, such that 1 >

Method and apparatus for input-buffered asynchronous transfer mode switching

Abstract: An ATM packet switching system has output segregated input buffers, which are operated on a realtime by crosspoint selection circuits implementing a combined buffer fill/age algorithm to come up with a new selection every packet cycle.

Circuit switching system for interconnecting logical links between packet switching networks

Abstract: A circuit switching system for interconnecting end point systems, such as packet switches, compressed voice concentrators, or data multiplexers, by allowing multiple logical links on each logical channel. The circuit switching system is connected to the end point system by a number of communication facilities with each facility having a plurality of logical channels. For packet switches, the circuit switching system is responsive to a first request to establish a first logical link on a logical channel to a packet switch and is responsive to a second request for another logical link to that packet switch to establish a second logical link on the same logical channel. The circuit switching system is responsive to a third request for establishing a logical link to another packet switch on the same logical channel for denying this request and for negotiating another logical channel.

Congestion control method and apparatus for end-to-end packet communication

Abstract: In a packet switched communications system wherein each destination data terminal sends an acknowledgment packet signalling correct receipt of packets from a source terminal, a congestion detector is provided for detecting a traffic congestion in the system to enable a packet detector. The packet detector, when enabled, detects the receipt of an acknowledgment packet from the destination terminal and stores this packet in a buffer for a specified period of time. The stored packet is then forwarded toward the source terminal upon termination of the specified time period.

Fast packet technology for future switches

Abstract: New network services other than the traditional voice communications between people will be increasingly bursty in bandwidth needs and will require distributed processing and control. The new fast packet technology for transmission and switching is ideally matched to these future network service needs. In this paper, we give a high-level sketch of the evolution of fast packet switch technology starting with the first packet switches and ending with some architectures that offer promise as potential switching vehicles for Broadband ISDN. We shall be using examples of AT&T experimental switch architectures to illustrate the evolution and technical capabilities.

Packet recovery and error correction in high-speed wide-area networks

Abstract: The author presents a novel technique for reducing packet loss rate in high-speed wide-area networks in which the BER (bit-error rate) is low. Grouping packets into blocks and adding a packet that computes parity over bits of all packets in a block allow a data recipient to reconstruct any single packet in a block, using the other packets and the block parity packet. The missing packet is identified by observing a sequence-number gap in the stream of incoming packets. Adding another packet containing parity information over the diagonals of a series of blocks allows the decoder to correct a single bit error and reconstruct a missing packet, both occurring in the same block. The performance of the scheme was evaluated using a model of a single-server, discrete-time, finite-capacity queue. It was found that, if the input rate of packets to the queue is such that the packet rejection probability is 10/sup -3/ and below, it is possible to find a proper value of block size for which the decoding yields a substantial reduction in packet loss rate. Further reductions are possible if the server discards not necessarily newly arrived packets but takes into consideration their block affiliations and attempts to distribute the rejected packets among the blocks to maximize the decoding capability. >

Burst switching-an update

Abstract: Burst switching research in dispersed control and integrated switching is described. Burst transport is integrated in that voice and data are switched through the same switching fabric and transmission media. Burst switching is compared to and distinguished from fast packet, fast circuit, and ATM (asynchronous transfer mode) switching. Misunderstandings about burst transport that have appeared in the literature are corrected, to wit: burst does not immediately clip in case of channel contention; burst switches voice and data in the same way; and a burst switch interfaces naturally to other types of switches. Round-trip delay performance is calculated to be less than 5 ms. The current status of the burst project is described. >

Performance of a non-blocking space-division packet switch with correlated input traffic

Abstract: The performance of nonblocking space-division packet switches in a correlated-input traffic environment is investigated. In constructing the input traffic model, it is considered that each input is a TDM (time division multiplexing) link and connected to multiple sources. A call experiences the alternation of active and inactive periods, and periodically generates packets while in the active period. All the packets generated by each call are assigned to the same output. The output address of each call is assumed to be uniformly assigned. In this multimedia correlated-input traffic environment, it is shown that the maximum throughput of the switch is always bounded by 0.500 >

Communication system having a packet structure field

Abstract: A communication system develops an information packet (309) having a packet structure field (G) and at least one message. The message has an address (H) and information (I) associated with the address. A central station (302) accumulates and incorporates the at least one message into the information packet. The central station determines the occurrence of the at least one address and generates identifying data (435) indicating where the address occurs within the information packet. The identifying data is incorporated into the packet structure field and the information packet is transmitted. The information packet is received by at least one selective call receiver (310) capable of operating in a high power mode in order to receive the information packet and a low power mode when receiving is not being performed. The selective call receiver extracts the packet structure field and interprets the identifying data.

Buffer memory device for packet data and method of controlling the device

Abstract: A buffer memory device and method for fixed-length packet data. The write and read addresses of a memory are controlled by respectively independent pointer queues and these pointer queues are arranged to be distributed to the address data queue of any of the packet queues. When data are concentrated on a specific packet queue, the address data of packet queues low in use frequently are distributed so that the writable area of the specific packet queue can be expanded.

Queueing analysis of delay constrained voice traffic in a packet switching system

Abstract: Unlike data traffic, the voice packet stream from a node has very high correlation between consecutive packets. In addition, in order for the speech to be properly reconstructed, a delay constraint must be satisfied. A queueing model that accurately predicts packet loss probabilities for such a system is presented. Analytical results are obtained from an embedded bivariate Markov chain and are validated by a simulation program. Based on this model, the impact of the delay constraint, talkspurt detection thresholds, and packet size on packet loss are studied. Two schemes, named 'instant' and 'random', for discarding late packets are considered. Simulation results show that better performance can be obtained by using the latter scheme. >

A neural network implementation of an input access scheme in a high-speed packet switch

Abstract: A neural network implementation of an input access scheme in a high-speed packet switch for broadband ISDN (integrated services digital network) is presented. In this switch, each input maintains a separate queue for each output; thus, in an (n*n) switch there will be n/sup 2/ input queues. Using synchronous operation, at most one packet per input and output will be transferred at every slot. A neural network maximizing the throughput of this switch is determined, and the form of the energy function, its optimized parameters, and the connection matrix are given. Simulations with random inputs have yielded results close to optimal throughput. This neural network can be implemented with the existing technology for medium switching sizes. >

Performance analysis of a growable architecture for broadband packet (ATM) switching

Abstract: The authors examine a growable architecture for broadband packet (asynchronous transfer mode) switching, consisting of a memoryless, self-routing interconnect fabric and modest-size packet switch modules, proposed by K.U. Eng et al. (1989). They focus on the cell loss probability, because the architecture attains the best possible delay-throughput performance if the packet switch modules use output queueing. They compute an upper bound on the cell loss probability for arbitrary patterns of independent cell arrivals, possibly including isochronous circuit connections, and show that both sources of cell loss can be made negligibly small. For example, to guarantee a cell loss probability of less than 10/sup -9/, this growable architecture requires packet switch modules of dimension 47*16, 45*16, 42*16, and 39*16 for 100%, 90%, 80%, and 70% traffic loads, respectively. The analytic techniques used to bound the cell loss probabilities are applicable to other output queueing architectures. >

Node for a fast packet-switching network in optical-electrical technology

Abstract: A node for a fast packet-switching network in optical-­electrical technology comprises an optical switching matrix (MOT) and an electrical control equipment (EC) which processes the signalling and the information packet headers. More particularly, the control equipment updates the label and, depending on such a label, searches for the routing through the node. A centralized node controller (CEL) processes the signalling, while a distributed processing system (PEE) processes the packet headers and routes the packets through the network. For all communications in progress, the distributed processing system (PEE) periodically forwards routing requests towards an electrical self-routing switching matrix (MEL) associated with the optical matrix (MOT); when a connection path has been found between an input and an output of the electrical matrix (MEL), the same path is reproduced in the optical matrix (MOT) and the packets are transferred towards the node output through the optical matrix.

Routing method for fast packet switching systems

Abstract: A fast packet switching system comprises an interconnection network associated with a distributed control structure composed of a plurality of processing units (UC1-1 ... UC3-16) managing the routing at the virtual call level. At least some of said processing units associated each with a group of network inputs/outputs store bandwidth occupancy data relevant to the interstage links which can be reached from the inputs of said group and are included between said inputs and a central network stage where there is a maximum number of alternative paths or, respectively, bandwidth occupancy data relevant to interstage links which lead to the outputs of said group and are included between said stage and the output, said data being updated whenever a new call is routed. When a virtual call is to be routed, the processing units associated with the input or respectively the output involved in the connection, evaluate each, on the basis of the up-to-date conditions of bandwidth occupancy and of the bandwidth requirements of the new call, a cost function of the connection along the portion of each of the possible routing paths included between the input and the stage where there is the maximum number of alternative paths, or respectively for the portion of each routing path included between such stage and the output; the results of the evaluations carried out by said units are combined together in one of the units which determined a global cost function for the individual connection paths and forwards the call on the path presenting the minimum cost function.

Circuit allocation and overload control in a hybrid switching system

Abstract: A hybrid switching system which provides integrated packet and circuit switching is considered. The framing structure is based on position multiplexing of the isochronous slots. The switch capacity is dynamically allocated to meet the demand of the synchronous circuits. Due to some wastage inherent in the framing structure, not all of the remaining capacity is available for the packet switched traffic. In order to evaluate the packet capacity, we derive the statistics of the effective bandwidth utilized by the isochronous traffic. Three circuit allocation policies are considered: repacking, first-fit and first-fit involving circuit blocking policy. The analysis takes into consideration the waste created by these policies. Numerical results are presented to compare between the efficiency of these schemes, and to demonstrate, in each case, the effect of circuit loading on the effective capacity utilized by the isochronous traffic which in turn determines the packet capacity.

Packet video transmission through ATM networks

Abstract: The basic aspects of packet video transmission technology are described, and some new results are presented. The advantages of packet video transmission through ATM (asynchronous transfer mode) networks and items to be solved are discussed from both the network and the user sides. Modeling methods, including burstiness measures are described. Examples of modeling based on the Markov modified Poisson process are shown. Packet loss protection and recovery methods are discussed, and the effects of a layered coding scheme are described. Subjective picture quality based on variable rate video transmission is demonstrated. >

A survey of fast packet switches

Abstract: With the advent of optical fiber and its large bandwidth, many services, such as packetized data, voice, and video, are now becoming available on physical transmission lines. The high data rates, however, have created a demand for high speed switching. Included among the different strategies which have been proposed are fully- and non-fully-connected switches, intelligent and non-intelligent switching nodes, broadcast capability, input and output queueing, input concentration and output reentry, and path preallocation. Most switches have a modular design. This paper compares the Knockout Switch [1], a switch designed by Jonathan Turner [2, 3], a switch designed by Joseph Hui and Edward Arthurs [4], and the Starlite Switch [5] based on the strategies listed above. Advantages and disadvantages are cited and conclusions have been made about the tradeoffs involved with operating conditions. Finally, future issues affecting fast packet switching are described.

Nonblocking networks for fast packet switching

Abstract: An extension of the classical theory of nonblocking networks is identified and studied that is applicable to multirate circuit and fast packet/ATM switching systems. Conditions are determined under which the Clos, Cantor, and Benes networks are strictly nonblocking. Conditions are also determined under which the Benes network and variants of the Cantor and Clos networks are rearrangeable. It is found that strictly nonblocking operation can be obtained for multirate traffic with essentially the same complexity as in the classical context. >