Showing papers on "Fast packet switching published in 1990"

Fast packet switch architectures for broadband integrated services digital networks

Abstract: Background information on networking and switching is provided, and the various architectures that have been considered for fast packet switches are described. The focus is solely on switches designed to be implemented electronically. A set of definitions and a brief description of the functionality required of fast packet switches are given. Three basic types of packet switches are identified: the shared-memory, shared-medium, and space-division types. Each of these is described, and examples are given. >

Switching and Traffic Theory for Integrated Broadband Networks

Abstract: 1. Integrated Broadband Services and Networks-An Introduction.- I: SWITCHING THEORY.- 2. Broadband Integrated Access and Multiplexing.- 3. Point-to-Point Multi-Stage Circuit Switching.- 4. Multi-Point and Generalized Circuit Switching.- 5. From Multi-Rate Circuit Switching to Fast Packet Switching.- 6. Applying Sorting for Self-Routing and Non-Blocking Switches.- II: TRAFFIC THEORY.- 7. Terminal and Aggregate Traffic.- 8. Blocking for Single-Stage Resource Sharing.- 9. Blocking for Multi-Stage Resource Sharing.- 10. Queueing for Single-Stage Packet Networks.- 11. Queueing for Multi-Stage Packet Networks.

Packet recovery in high-speed networks using coding and buffer management

Abstract: A technique for fiber-optic networks based on forward-error correction (FEC) that allows the destination to reconstruct missing data packets by using redundant parity packets that the source adds to each block of data packets is presented. Methods for generating several types of parity packets are described, along with decoding techniques and their implementations. Algorithms are presented for packet interleaving and selective rejection of packets from node buffers, both of which disperse missing packets among many blocks, thereby reducing the required coding complexity. Performance evaluation, by both analytic and simulation models, shows that this technique can result in a reduction of up to three orders of magnitude in the packet loss rate. >

Method and apparatus for packet communications signaling

Abstract: A packet format for accurately transporting signaling information in a packet network is described. The packet format comprises a burst count, a sequence number, a burst time, and a signaling status bit. The burst count is for indicating a burst to which the packet belongs. The sequence number is for identifying a first packet of the burst. The burst time is for selectably indicating (1) a time delay from onset to a packet node bus for the first packet of the burst and (2) a time interval between successive signaling bit transitions.

N-Way Conferencing with Packet Video

Abstract: : Packet switching technology promises to allow improvement of video quality by efficiently supporting variable-rate video coding. Its inherent multiplexing of multiple streams also allows more efficient multi-destination delivery for N-way conferencing. However, most commercial video codecs are designed to work with circuits, not packets, in part because these benefits are accompanied by some problems. This paper describes a packet video system implementation in which commercial codecs were adapted to exploit the benefits of packet switching while addressing the problems as follows: 1) clock synchronization was obviated by asynchronous operation; 2) delay was reduced by bandwidth reservation and fast packet forwarding; and 3) packet loss was reduced by bandwidth reservation and forward error correction. An overview of the system is followed by sections addressing each of the problems and benefits, plus future directions for expansion of the system.

Packet address look-ahead technique for use in implementing a high speed packet switch

Abstract: Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). Each incoming packet cell has added thereto an additional header field containing information identifying a particular output module and a particular output port of that module. An input module associated with the switching crosspoints changes the additional header information to identify the particular output module of the next subsequent packet cell.

Congestion-free transmission of real-time traffic in packet networks

Abstract: The process of packet clustering in a network with well-regulated input traffic is studied. Based on this study, a strategy for congestion-free communication in packet networks is proposed. The strategy provides guaranteed services per connection with no packet loss and an end-to-end delay which is a constant plus a small bounded jitter term. Therefore, it provides an attractive solution for the transmission of real-time traffic in packet networks. The strategy is composed of an admission policy imposed per connection at the source node and a particular queuing scheme, called stop-and-go queuing, practiced at the switching nodes. The admission policy requires the packet stream of each connection to possess a certain smoothness property upon arrival to the network, while the queuing scheme eliminates the process of packet clustering and thereby preserves the smoothness property as packets travel inside the network. Implementation of the stop-and-go queuing is simple, with little processing overhead and minor hardware modifications to the conventional FIFO (first in, first out) queuing structure. >

Dual port memory buffers and a time slot scheduler for an atm space division switching system

Abstract: An asynchronous transfer mode switching network system relays packets stored in packet buffer units to output ports designated by the packets, and a time slot scheduling unit assigns time slots to the packets stored in the packet buffer units upon arrival at the packet buffer units for preventing the packets from collision in a space division switching unit, wherein each of the packet buffer units sequentially writes new packets into respective memory locations but randomly reads out the new packets in the time slots assigned by the time slot scheduling unit so that the throughput of the space division switching unit is improved.

Packet switch communication network using packet having virtual channel identifier

Abstract: In a packet network which includes a plurality of packet switching stations and in which a packet including in its header portion a VPI (Virtual Path Indentifier) for identifying one of logical paths multipliexed on a transmission line and a VCI (Virtual Connection Identifier) for identifying one of logical connections multiplexed on one logical path is communicated between the switching stations, each switching station preliminarily designates a VCI to be given to a packet directed to that station when a logical connection is to be set up between that station and another station. When receiving an information packet from the other station, the each station makes access to header label conversion tables on the basis of a VCI included in the received packet to read internal routing information necessary for a packet switching operation and a VCI to be given to a packet to be delivered.

Switching network architecture for atm based broadband communications

Abstract: Being the communication core of future broadband products, the ATM based switching network architecture must comply with a challenging set of future safe requirements and objectives, which are tentatively defined first. After some period of research work, a number of different solutions for fast packet switching or ATM switching are still proposed. It is thus interesting to discuss the respective attributes of key architecture options for asynchronous switch fabrics. As an illustration, the paper then describes a new ATM based switching architecture for asynchronous communications based on the advantageous combination of a multiple-path self-routing principle with an internal transfer mode using multi-slot cells. These principles are the foundation for a flexible and fault tolerant switching network configuration built with two Weis of standard switching components: the Switch Module board equivalent to a 128 x 128 single-stage matrix operating at 150 Mbit/s, and the Integrated Switching Element LSI circuit realizing an elementary, fully featured, 32 x 32 switching matrix.

Wireless in-building telecommunications system for voice and data communications

Abstract: A wireless in-building telecommunications system for voice and data communications is disclosed having at least one node (101) arranged for linking to the PSTN (151) and at least one digital information source (153, 155, 157, 159) multiplicity of user modules (103) (UM's) linked to the node via a shared RF communications path (107). Each UM is coupled to a voice telephone instrument (127) and to one or more data terminals (165). The UM's communicate with the node by exchanging fast packets via the common RF path (107). The node also includes a fast-packet-switched mechanism controlled by a bandwidth allocating scheme to prevent collisions of packets as they are transmitted between the various units (101, 103) (nodes and/or user modules) that may be accessing the RF path (107). Also disclosed is a method for allocating the required bandwidth to each of the users of the common communications path in a wireless in-building telephone system. The invention provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. It also synchronizes the transfer of the data and the allocation of bus bandwidth.

Locally-optimal deflection routing in the Bidirectional Manhattan Network

Abstract: A class of shortest-path distributed-routing techniques is presented, and the authors show a locally optimal solution under uniform traffic assumptions. It is argued that, as the number of nodes grows to infinity, the throughput tends to the limit represented by the maximum throughput attainable with the store-and-forward technique and infinite queueing storage. The results obtained show the suitability, as far as the throughput is concerned, of meshed networks using packet switching without storing packets at nodes. The routing techniques investigated perform similarly. At least one of these is simple enough to be implemented with very-fast circuitry, able to cope with the speed foreseen in future metropolitan-area networks (MANs). >

Basic element for the connection network of a fast packet switching node

Abstract: Basic element for the interconnection network of a fast packet switching node, where a synchronization is made at bit input stream level, the cell beginning is identified and a stream conversion from the serial form to a word parallel form is performed. Cells are thus transformed in a completely parallel form and in the same form they are cyclically discharged in the subsequent cell time in a memory (BC), where cells are written and read in a shared way on the basis of instructions given by a control unit (CC), thus performing the switching function. The control unit is essentially based on the use of a content-addressed associative memory, where a fraction of the routing header and a code indicating the time sequence on which the cells arrive are stored. Memory outgoing cells are reconverted from a completely parallel form to a form having the length of one word and therefore in a completely serial form at a bitrate equal to the input one.

A broadband optical multicast switch

Abstract: We propose a new optical muhicast switching system based on a two-phase contention resolution algorithm This architec ture may simultaneously support packet switching, and circuat channel emulation. It can handle time-multiplexed variable bit rate random access packets and reserved access packets in a single framework that incorporates unicast and multicast switching. We present the overall switch architecture, its optical device requirements, and possible implementation schemes. Performance enhancements through the addition of multiple tracks are discussed which indicate the flexibility inherent in this design. Results of an analysis of the throughput and switch performance are discussed.

An analysis of 'hot-potato' routing in a fiber optic packet switched hypercube

Abstract: Two implementations of a fiber-optic packet-switched hypercube are proposed. In the first, each directed link is implemented with a fixed wavelength laser and photodetector, and all optical transmissions are wavelength multiplexed onto one or more fibers. In the second, the electronic crosspoint matrices within the nodes are eliminated by allowing each laser to be tunable over a range of log N wavelengths. Assume that a hot potato, or deflection, routing algorithm is used; as soon as a packet is received at a node, a routing decision is made and the packet is sent out. The node attempts to send the packet towards its destination. The analysis indicates that a hypercube, hot-potato routing offers essentially optimal performance for random traffic, regardless of how large the hypercube grows, and it significantly outperforms traditional shortest-path routing with buffering and flow control. A few variations, including an algorithm which gives priority to packets closer to their destinations and one which gives priority to various classes of traffic, are also proposed and analyzed. >

An atm switching system based on a distributed control architecture

Abstract: An ATM switching system architecture is presented which employs distributed control to cope with diversified requirements. ATM switching system is expected to efficiently and flexibly handle multimedia traffic, therefore traffic control architecture is one of the most crucial issues for ATM switching systems. The requirements, architectural concept and construction scheme of two important technologies, self-routing switches and quality control of statistical switching, are discussed. A switch fabric, which provides a unified inter-module inter face, switches and distributes cells between modules. It gives very stable switching performance under an arbitrary flow environment without centralized resource management. A three-layerd traffic control model is also presented which consists of cell transfer level, call control level and network control level. Control functions of each level and the interfaces among them are considered, then cell transfer level control schemes and their performances are discussed, including marking scheme for policing control and the effect of burstiness. Laboratory experiment system is designed and implemented to confirm the feasibility of the ATM switching system architecture concept. The system employs a VLSI memory switch with dynamic link speed control as an element of the self-routing switch fabric, achieving the capacity of 256 I55Mb/s lines. It also realizes efficient statistical switching functions such as policing control, multiplexing and quality control for multiple transport quality classes.

Survey of switching techniques in high-speed networks and their performance

Abstract: The major ATM switch architectures and their improvement techniques are categorized and discussed, focusing on performance issues. The performance measures of interest are the maximum throughput, the delay time, and the cell loss probability. The major assumptions and notations used are summarized. A survey is presented of nonblocking switches and their improvement techniques. The performances of a variety of nonblocking switches are compared. >

Hybrid switching system for a communication node

Abstract: The hybrid packet and circuit switching system allows merging of packet and circuit traffic from user interface modules on a TDM bus and transfer of packet information from one module to another module or the exchange circuit information between modules. Circuit exchanges or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. A routing indication common to the packet and circuit bursts is used for controlling the switching of the bursts by the switch 1. The indication is performed by piggy backing the target module address for the circuit bursts, as well as for the packet burst, with the data bursts. Marking tables needed for the circuit burst allocation are located in the user interface modules.

A rate-based congestion avoidance and control scheme for packet switched networks

Abstract: A congestion avoidance and control scheme that monitors the incoming traffic to each destination and provides rate-based feedback information to the sources of bursty traffic so that sources of traffic can adjust their packet rates to match the network capacity is described. The congestion avoidance mechanism at nodes on the periphery of the network controls incoming traffic so that it does not exceed the capacity of paths to different destinations. The congestion control mechanism at each node monitors the performance of adjacent links and generates rate control messages that warn the sources of traffic before congestion develops. Some existing schemes are reviewed, and the congestion avoidance and control scheme and its applicability to various transport protocols are discussed. Experiments show that the scheme is effective in preventing congestion inside the network and that it manages to restrict the traffic on any overloaded path to 80%-90% of its capacity. >

Lightnet: lightpath based solutions for wide bandwidth WANs

Abstract: An inherent problem of conventional point-to-point wide area network (WAN) architectures is that they cannot translate optical transmission bandwidth into comparable user-available throughput due to the limiting electronic processing speed of the switching nodes. A solution to wavelength division multiplexing (WDM)-based WAN networks that addresses this limitation is presented. The proposed lightpath architecture trades the ample bandwidth obtained by using multiple wavelengths for a reduction in the number of processing stages and a simplification of each switching stage, leading to substantially increased throughput. The principle of the lightpath architecture is the construction and use of a virtual topology network in the wavelength domain, embedded in the original network. A study is made of the embedding of virtual networks whose topologies are regular, using algorithms which provide bounds on the number of wavelengths, switch sizes, and average number of switching stages per packet transmission. >

Large scale atm multi-stage switching network with shared buffer memory switches

Abstract: This paper discusses the configuration of an ATM(Asynchronous Transfer Mode) switching network with a shared buffer memory switch (SBMS) which has the potential to provide good traffic characteristics and easy LSI implementation. The scaling factors of the ATM switching network under a condition of mixed applications are discussed first. Then the SBMS as the unit element ofthe multi-stage switching network is described, and its performance evaluation and experimental data are introduced. The data indicate excellent performance under burst cell arrival condition. Last a concept of a large scale ATM switching network configuration with multi-stage switches is proposed. The non blocking condition in ATM multi-stage switching network as an alternative resource management scheme is described.

Protocol conversion system

Abstract: An X.25 protocol apparatus can communicate with another X.25 apparatus or a X.32 apparatus through a telephone network, an ISDN network, or a PBX network, by attaching protocol conversion system to the X.25 apparatus. The conversion system has a pair of signal identification portions (1, 6) for separating a receive packet to a data packet and a control packet, a call process portion (3, 12) for dial signal process, and an address table (4) and a packet edition portion (5) for address conversion of a control packet. A data packet is forwarded from one signal identification portion to another signal identification portion through direct path (53). A control packet is forwarded to a control packet identification portion (2) for control process which includes dial signal process, address conversion, and protocol sequences. This system is applicable to couple a data communication network which has a X.32 correspondence portion to another data communication network.

Efficient traffic performance strategies for packet multiplexers

Abstract: We show that in performance modeling of packet communication systems, the periodicity of the traffic stream cannot be ignored. In addition to degrading overall performance, for common buffer management strategies such periodicity is shown to result in successive packet losses for certain sources. Alternative strategies are proposed to alleviate such problems. Some insights about the “relevant time interval” for modeling of the traffic are also obtained.

A 3-stage interconnection structure for very large packet switches

Abstract: Proposes a three-stage broadband packet-switch architecture for a future central office with more than 16000 ports. The switch is constructed by interconnecting many small independent switch modules, which can be implemented using modifications of various well-studied switch fabric designs. Multiple paths are provided for each input-output pair, and the channel grouping technique is used to decrease delay and increase throughput. A datagram packet routing approach is adopted in order to eliminate the table lookup that will be required by virtual-circuit routing. Ways of guaranteeing the sequence integrity of packets are discussed. It is estimated from performance analyses that 32768-port switches can be constructed and can perform well based on switch fabrics of no more than 128 ports. >

Optically-processed routing for fast packet switching

Abstract: Electronic routing control of photonic switches is considered. The types of network architectures and routing strategies that the authors think are best-suited to optical processing are proposed, and a generic optical routing processor is described. Address-encoding schemes for optically controlling a photonic switching node are presented. The results of several experiments that have demonstrated optical control of a photonic switching node are reported. Potential applications of these photonic switching architectures are described. >

Growable packet switch architecture

Abstract: This invention is large N×N packet switch, formed using a plurality of smaller packet switches. The invention comprises an N input, L output interconnect fabric (L>N), and a plurality of J×K smaller packet switches (J>K). Each of the J inputs to each packet switch is connected to a separate one of the L outputs of the interconnect fabric, and each of the K outputs from each packet switch is connected to a destination equipment. In operation, packets are received at the N inputs to the interconnect fabric, and each packet is routed to one of the inputs of the packet switch associated with the destination user equipment for the packet. Simultaneous packets, up to J in number, are routed to separate inputs of a particular packet switch for distribution to their respective destinations, while all other simultaneous packets destined for user equipments associated with the same packet switch are lost, the probability of such a loss being acceptably small.

Packet switching system having bus matrix switch

Abstract: A packet switching system having a matrix switch including input packet transfer buses and output packet transfer buses. Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.

Queueing strategies for multicast packet switching

Abstract: The authors consider multicast packet switching where an input may send the same packet to many outputs within an ATM (asynchronous transfer mode) time slot. A host of multicast queuing disciplines can be exercised. Assuming only independent HOL (head of line) service to an output from slot to slot, the delay performance and saturation throughput are derived. The accuracy of the assumption for different disciplines is examined via extensive simulation. It is shown that the FCFS (first come, first serve) HOL service discipline not only has almost completely identical results for simulation versus analysis, but also provides the best saturation throughput, fairness, and delay performance among all disciplines considered. The analysis shows that implementing packet priorities can significantly improve delay performance. It is concluded that offering priority according to age in the queue is a worthwhile feature for multicast (as well as unicast) packet switches. >

Fast connection establishment in high speed networks

Abstract: Protocols for establishing, maintaining and terminating connections in packet switched networks have been studied in the literature and numerous standards have been developed to address this problem. In this paper, we reexamine connection establishment in the context of a fast packet network with an integrated traffic load, explain why previously proposed solutions are inadequate and develop a protocol for connection establishment/takedown that is appropriate for such a network. The underlying model that we use is the recently developed PARIS network, though our ideas are sufficiently general to cover many other fast packet networking architectures.

A CMOS Batcher and Banyan chip set for B-ISDN packet switching

Abstract: A Batcher and Banyan chip set suitable for broadband packet switch applications is described. Each chip concurrently processes 32 bit-serial packet channels and is a building block for larger networks. Current chip samples have been tested at channel rates of 170 Mb/s in 1.2- mu m double-metal single-poly CMOS for both the Batcher and Banyan chips. Each chip requires a 5-V supply, dissipates approximately 1.5 W, provides 5.44 Gb/s of switching capacity, can process 12.8 million asynchronous transfer mode (ATM) cells per second, and is packaged in an 84-pin leadless ceramic chip carrier (LCCC) for convenient testing. The design and implementation of the switching elements capable of supporting the high-speed bit-serial channels and the chip architectures that accommodate them are described in detail. >