Showing papers on "Fast packet switching published in 1993"

System for securing inbound and outbound data packet flow in a computer network

Abstract: A filter module allows controlling network security by specifying security rules for traffic in the network and accepting or dropping communication packets according to these security rules. A set of security rules are defined in a high level form and are translated into a packet filter code. The packet filter code is loaded into packet filter modules located in strategic points in the network. Each packet transmitted or received at these locations is inspected by performing the instructions in the packet filter code. The result of the packet filter code operation decides whether to accept (pass) or reject (drop) the packet, disallowing the communication attempt.

Feedback control of congestion in packet switching networks: the case of a single congested node

Abstract: Addresses a rate-based feedback approach to congestion control in packet switching networks where sources adjust their transmission rate in response to feedback information from the network nodes. Specifically, a controller structure and system architecture are introduced and the analysis of the resulting closed loop system is presented. Conditions for asymptotic stability are derived. A design technique for the controller gains is developed and an illustrative example is considered. The results show that, under appropriately selected control gains, a stable (nonoscillatory) operation of store-and-forward packet switching networks with feedback congestion control is possible. >

Packet-based data compression method

Abstract: A data processing system is described that employs data packets which include at least static and dynamic fields, the static fields containing information that often remains constant during a multi-packet communication interval and the dynamic fields containing information that changes for each packet. Many packets also include a user-data fields. A compression method is described which comprises: reformatting each data packet by associating its static fields with a first packet region and its dynamic fields with a second packet region. The process then assembles a static table that includes static information from at least an initial data packet's first packet region. It then identifies static field information in a subsequent data packet's first packet region that is common to the information in the static table. Such common information is encoded so as to reduce its data length. The common static information is then replaced in the modified data packet with the encoded common static information and the modified data packet is then transmitted. A similar action occurs with respect to user-data information. A single dictionary table is created for all packet headers, while separate dictionary tables are created for each user-data portion of a packet-type experienced in the communication network thereby enabling better compression.

Frame-based transmission of data

Abstract: A network for transferring packet data in a frame structure, preferably mixed with isochronous data is provided. The frame structure is a continuously repeating structure, with each frame having a number of time slots. Certain ones of the time slots are available for transmitting packet data. The packet data is re-timed, e.g., by using a FIFO to output the data nibble-wise as required by the frame structure. Similar re-timing can be used for isochronous data so that the frame structure defines time-division multiplexing of the packet data and isochronous data. A four/five encoding scheme provides sufficient encoding efficiency that both the packet data and other data can be accommodated without degrading the data rate of the packet data. The encoding scheme provides extra symbols which can be used for transferring "no carrier" information, or "frame alignment" messages. Preferably, the frame structure is translated to and from a packet structure to permit the present invention to be used with previously available packet circuitry such as a media access controller and a hub repeater circuit. Latency of the FIFO can be reduced by pre-filling with packet preambles, and/or sub-latency propagation of preamble bytes, or providing special MACs which do not output preambles, and using the buffer circuitry to output preambles.

Photonics in Switching

Abstract: Multiwavelength Switching and Interconnection Networks. Optical Code-Division Multiple Access. Space Division Switching. Free-Space Interconnection Techniques. Switching Systems-Time and Wavelength Division. Photonic Fast Packet Switching. Multi-Dimensional Switching Systems. Index. Chapter References.

Method and system for the arrangement of vocoder data for the masking of transmission channel induced errors

Abstract: A method and system (16) by which parameter data representative of vocoded speech are organized into a data packet for transmission so as to reduce the impact of transmission channel induced errors on the data packet. A data packet is constructed with certain most perceptually significant bits of parameter data at the beginning of the data packet. Following in the data packet are lesser perceptually significant bits of the same parameter data. Other parameter data then follows in the data packet. Interleaved in the data packet following the most perceptually significant bits at the beginning of the data packet are most perceptually significant bits of other parameter data. A parity check code is computed from the most perceptually significant bits in the data packet and also interleaved in the data packet following the most perceptually significant bits at the beginning of the data packet.

Addressing technique for storing and referencing packet data

Abstract: A hierarchical addressing technique is employed in a packet communications system to enhance flexibility in storing and referencing packet information. This method permits packet message data and certain packet control data to be stored in memory locations without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets received or to be transmitted.

Architectures for ATM switching systems

Abstract: Eight specific architectures for asynchronous transfer mode (ATM) switching systems are compared: the Knockout, Sunshine, Lee's, Tandem Banyan, Shuffleout, and three variations on buffered Benes networks. The differences between switching systems, based on architectural choices rather than details of implementation are discussed. Several broad categories of systems based on high-level architecture choices are considered. Within each category one or more alternatives are reviewed, and an equation for the chip count for each alternative is developed. The equations are used to make plots of chip count for each network over a range of parametric values. >

Packet reassembly during cell loss

Abstract: Asynchronous transfer mode (ATM) is a packet switched data transport system based on short, fixed length cells. Each cell carries a virtual channel indicator (VCI) and virtual path indicator (VPI) in its header. Essential to the services offered by the ATM networks is the ATM adaptation layer (AAL), an ITU-TSS defined layer that adapts the cell-based ATM physical layer to packet, datagram, or bit-stream-oriented higher layers. Failure modes causing cell loss along a virtual connection are examined, and the ways AALs cope are analyzed. The sources of cell loss and their effects on AAL3/4 or AAL5 type of service are described. The usefulness of the ability of AAL3/4 to pass fragments of corrupted data up to higher layer protocols is discussed, and the implementation of selective cell discarding within switching nodes is considered, and the limitations imposed by each AAL are examined. >

Packet switch to provide code division, multiple access cellular service

Abstract: A system for relaying CDMA packetized data from a cell site or sites to a destination speech processor. The CDMA packetized data, is received at the cell site and is sent in its packetized form along with a destination address to a packet switch. A packet handler at the packet switch receives the CDMA data packets and forwards them on a packet bus. If the destination speech processor assigned to that call is connected to the packet bus, it recognizes its own address and processes the data packet.

Method and system for real-time burstiness analysis of network traffic

Abstract: Method, for use with a communications network, for measuring and analyzing the burstiness of network traffic based on the ratio of packet interarrival times. The network traffic includes at least one data burst, and each data burst includes a stream of data packets for travel over the network. The method includes (a) receiving a first data packet of the at least one data burst for travel over the network, the first data packet having an associated first packet interarrival time, and (b) consecutively receiving a second data packet for travel over the network, the second data packet having an associated second packet interarrival time. The method also includes (c) determining the ratio of the second packet interarrival time to the first packet interarrival time and (d) comparing the ratio of the second packet interarrival time and first packet interarrival time to at least one predetermined constant. Lastly, the method includes (e) determining whether the second data packet belongs to the at least one data burst based on the comparison, and (f) accumulating the second data packet with a data burst based on the comparison. A system for carrying out the method is also provided.

Improved queueing analysis of shared buffer switching networks

Abstract: The authors describe several methods for analyzing the queueing behavior of switching networks with flow control and shared buffer switches. They compare the various methods on the basis of accuracy and computation speed, where the performance metric of most concern is the maximum throughput. The best of the methods accurately predicts throughput for multistage networks constructed from large switches (>or=8 ports). >

Photonic fast packet switching

Abstract: Several approaches to photonic fast packet switching systems are presented. The wavelength-, time-, code-, and space-division approaches, including free-space photonic fast packet switching, are discussed. These approaches to photonic fast packet switching systems show that the research in this area is still in its infancy. Among various solutions, those based on a wavelength-division transport network and an electronic controller are most mature. >

Voice synchronization in packet switching networks

Abstract: An algorithm for voice synchronization for packet switching networks is presented. The algorithm has been tested both in simulation and on a real network. The algorithm runs on the TRAME packet switching network for both the Vocoder and CELP DoD voice coding standards. Some results of these tests are presented. Some details of the algorithm development and implementation are given as well. >

Unslotted deflection routing in all-optical networks

Abstract: When nodes of a communication network have identical input- and output-link capacities, it is possible to use as few as one packet buffer per link, if one is willing to deflect-or misroute-a subset of simultaneously arriving fixed-length packets from preferred to alternate output links. This scheme, known as deflection routing, can achieve very fast packet switching in regular networks and has been proposed as the basic routing and switching protocol of several all-optical networks. The performance models of deflection-routing networks that have appeared in the literature have assumed that time is slotted and packets arrive at nodes on time-slot boundaries. In practice, however, slotted operation is difficult to implement in all-optical networks. The present authors evaluate by simulation the performance of deflection routing in unslotted networks. The evaluations show a surprising degradation of throughput in unslotted deflection routing networks, compared to slotted networks, and reveal situations where severe congestion occurs. To overcome these limitations they propose the use of specific control mechanisms in unslotted networks that allow one to eliminate congestion and to improve substantially the network throughput. >

Performance evaluation of input and output queueing techniques in ATM switching systems

Abstract: Modeling alternatives for a fast packet switching system are analyzed. A nonblocking switch fabric that runs at the same speed as the input/output links is considered. The performance of the considered approaches are derived by theoretical analysis and computer simulations. Performance comparison between input queueing approaches with different selection policies are presented. Novel input and output queueing techniques are also proposed. In particular it is shown that, depending on the implementation, the input queueing approach studied in this paper achieves the same performance as the optimum (output) queueing alternative, without resorting to a faster packet switch fabric. >

SCOQ: a fast packet switch with shared concentration and output queueing

Abstract: A space-division, nonblocking packet switch with data concentration and output buffering is proposed. The performance of the switch is evaluated with respect to packet loss probability, the first and second moments of the equilibrium queue length and waiting time, throughput, and buffer overflow probability. Numerical results indicate that the switch exhibits very good delay-throughput performance over a wide range of input traffic. The switch compares favorably with some previously proposed switches in terms of fewer basic building elements used to attain the same degree of output buffering. >

Photonic 2*2 packet switch with input buffers

Abstract: A self-routing 2×2 photonic packet switch with two fibre-loop input buffers that provide output contention resolution is demonstrated. The switch uses high-speed electronic control that prioritises all switching and buffer operations and guarantees packet integrity while maximising throughput.

Gigabit per-second optical packet switching with electronic control

Abstract: Currently, with optical time division multiplexing, a switching node is operated at the peak transmission rate. For example, if the data transmission rate is 10 Gbps, the line cards in the switching circuit are also required to operate at this rate despite the fact that the switching node does not actually need to access the data at this rate. Thus, the electronics, which includes the line cards at the switching node, is expensive and less reliable than a low-speed design. In this invention the requirement of operating the switching node electronics at the high speed link bit rate is eliminated by encoding the packet header field at a lower rate than the information in the data field. As a result, the line cards need only operate at the lower header rate. This is possible because the switching node does not need to process the data portion of the packet, but only the header information. The high-speed data portion of the packet is not optically to electrically converted at the switching node, but it passes almost transparently through the switching node. The invention also discloses overlapping several logical networks on the same physical network.

Frame-Induced Packet Discarding: An Efficient Strategy for Video Networking

Abstract: In order to provide efficient frame loss guarantees for video communication over ATM-like fast packet switched networks, we propose a simple to implement, yet effective, strategy called Frame-Induced Packet Discarding (FIPD), in which, upon detection of loss of a threshold number (determined by an application's video encoding scheme) of packets belonging to a video frame, the network attempts to discard all the remaining packets of that frame. Performance simulations are shown to demonstrate the efficacy of the FIPD strategy; networks employing FIPD exhibit close to two-fold increase in the number of video channels that they can support.

Photonic header replacement for packet switching

Abstract: A new method of photonic header replacement for use in photonic packet switched networks is proposed and demonstrated. The method uses a packet format containing a period of CW light that is modulated to produce the new header. The packet format and timing remain constant from input to output.

Signaling method for packet network and system

Abstract: A method which achieves a reduction of the virtual channel connection delay time in signaling without using permanent virtual channels (PVC) and without performing wasteful allocation of signal bandwidth. When a transmission terminal transmits a packet, a packet transmission control section requests transmission of a signaling packet to a signaling transmission section. The signaling transmission section searches a VC and signal bandwidth table and sends out, when a virtual channel is registered and a required signal bandwidth is provided, a packet using the virtual channel. When the signal bandwidth is insufficient, it requests from the packet switching system only a sufficient signal bandwidth and then sends out the packet. When no virtual channel is registered, the signaling transmission section requests a signaling packet from the packet switching system. The table includes, for each destination address, a virtual channel timer for releasing the virtual channel applied thereto after the virtual channel is held for a predetermined period of time after completion of transmission, and a bandwidth timer for reducing the signal bandwidth after each predetermined interval of time after the completion of transmission. At each end of a packet transmission, the two timers are reset to a clock.

EMC-Y: parallel processing element optimizing communication and computation

Abstract: EMC-Y is a new processing element for highly parallel computers designed to achieve high performance parallel computation by fusing a dataflow mechanism and a von Neumann execution pipeline. We have already developed EMC-R, which is the processing element used in the EM-4 prototype. EMC-Y improves on EMC-R's packet communication performance, allowing it to tolerate a more network traffic. This paper presents the architecture of EMC-Y, concentrating on the principles of packet communication. EMC-Y uses an output packet buffer and optimal packet routing to improve the performance of packet sending and transferring. EMC-Y changes the memory access priority for input packet buffer operation to improve the performance of receiving packets. Since the EMC-Y processor not only improves the performance of packet input and output but also balances them, it can tolerate a large amount of traffic and can improve the execution performance. We evaluate the improvements of EMC-Y architecture using a clock level simulator. The results show that EMC-Y improves performance by 50% to 70% in several programs over EMC-R at the same clock speed.

Access control in multicast packet switching

Abstract: Access control and performance for multicast packet switching in a broadband network environment are studied. In terms of scheduling the transmission of the copies of the packet onto output ports, two basic service disciplines are defined: one-shot scheduling (all the copies transmitted in the same time slot) and call splitting (transmission over several time slots). As subcategories of call splitting, SS (strict-sense) specifies that each packet can send at most one copy to the destination per time slot, whereas WS (wide-sense) does not carry this restriction. A scheme called revision scheduling, which mitigates the head-of-line (HOL) blocking effect by sequentially combining the one-shot scheduling and the call splitting disciplines, is proposed. Output contention resolution implementations, in the form of combinational logic circuits designed to resolve output contentions arising in each of the call scheduling disciplines, are introduced. A neural-network-based contention resolution algorithm is proposed to demonstrate the improvement of the optimal scheduling. >

A Survey of Modern HighPerformance Switching Techniques

Abstract: The rapid evolution in the field of telecommunications has led to the emergence of new switching technologies to support a variety of communication services with a wide range of transmission rates in a common, unified integrated services network. At the same time, the progress in the field of VSLI technology has brought up new design principles of high-performance, high-capacity switching fabrics to be used in the integrated networks of the future. Most of the recent proposals for such high-performance switching fabrics have been based on a principle known as fast packet switching. This principle employs a high degree of parallelism, distributed control, and routing performed at the hardware level. In this paper, we present a survey of high-performance switch fabric architectures which incorporate fast packet switching as their underlying switching technique to handle various traffic types. Our intention is to give a descriptive overview of the major activities in this rapidly evolving field of telecommunications.

Circuit and method for alignment of digital information packets

Abstract: A frame aligner circuit (10) for aligning a plurality of information packet signals (F1-F4) received within a maximum starting time variation interval consists of a plurality of frame detectors (110), stretch circuits (130) and variable delay circuits (120) which are controlled by a synchronization signal generator (140,150) and a delay control circuit (160). The delay control circuit in one embodiment of the present invention delays each information packet signal for a duration of time defined by the start of the information packet signal and an interval of time following the start of a last received information packet signals. In this manner, each information packet signal is delayed a corresponding period of time to align (at FA₁ - FA₄) the plurality of information packet signals with respect to one another.

Performance analysis of parallel ATM connections for gigabit speed applications

Abstract: A system which uses multiple asynchronous transfer mode (ATM) virtual circuits operating in parallel in order to control two WAN hosts at gigabit speeds is studied. Packets in parallel channels can bypass each other, so reordering of packets before delivery to the host is required. Performance parameters of this system, including ATM channel delay, packet loss, and resequencing delay, are analyzed, using a model for an ATM channel that multiplexes ATM virtual circuits carrying bursty and nonbursty traffic. It is found that the mean and variance of packet delay through an ATM switch grow linearly with burst size, and that the delay distribution can be closely approximated by a normal distribution. It is shown that packet loss is log-linear in the ratio of buffer size to burst size, and for maximum bursts larger than 50 cells, a buffer size of twice the maximum burst size is sufficient to achieve packet loss probabilities less than 10/sup -9/. Resequencing delay is shown to be insensitive to burst size, but the variance is large and grows linearly with burst size. >