Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.

Wireless Receiver For Sorting Packets

Abstract: A wireless receiver that sorts packets including a packet detector, multiple correlators, and multiple packet processors. Each correlator correlates a received signal according to packet type. Each packet processor processes the received signal according to packet type. A signal power detector may be provided to initially qualify the received signal as containing a packet, and the correlators determine whether a packet is present. The correlators may be configured for sequential or simultaneous correlation. For the simultaneous correlator configuration, a correlation monitor is provided to monitor correlation results to determine if the received signal contains a packet, and if so, to determine packet type. A low SNR packet detector may be provided which correlates the received signal to detect weak packet signals. The signal power detector may be omitted, where the correlators simultaneously monitor the received signal while a correlation monitor continuously monitors correlation results for packet detection.

A packet switching network with multiple packet destinations

Abstract: A communication method and packet switching network in which self-routing packets are communicated to a single-destination port of the switching network, a plurality of grouped destination ports or to two distinct destination ports after the modification by the switching network of the self-contained routing information within the packets. The packet switching network has a plurality of stages with each stage comprising a plurality of switch nodes, and the communicated packets can be of the single-destination, broadcast, or multiple-destination types of packets. The routing information within the packet comprises pairs of data bits with each pair associated with a stage of the switching network and with the value of the pair of bits determines the type of packet for the corresponding stage. Each switching node has two input and two output terminals, and a switch node in a particular stage is responsive to a single-destination packet received on an input terminal to communicate the packet to the output terminal designated by the value of the pair of bits for that stage. A switch node is responsive to a broadcast type packet to communicate the packet to both output terminals.

Efficient traffic performance strategies for packet multiplexers

Abstract: We show that in performance modeling of packet communication systems, the periodicity of the traffic stream cannot be ignored. In addition to degrading overall performance, for common buffer management strategies such periodicity is shown to result in successive packet losses for certain sources. Alternative strategies are proposed to alleviate such problems. Some insights about the “relevant time interval” for modeling of the traffic are also obtained.

Packet flow control method

Abstract: A packet flow control method where delay data are added into an initial packet as it traverses a packet switching network, and where the receiver of the initial packet, rather than the sender, establishes a window size based on such delay data to be used for the duration of a packet connection through the network The delay data allow for the calculation of an average rather than an instantaneous network delay such that the flow control mechanism is not dependent on the magnitude of network congestion that happens to be present when the connection is first established Since the receiver determines the window size, the flow control mechanism is put in place as an integral part of the initial packet exchange used to establish the two-way packet connection rather than requiring an additional packet communication to the receiver after a window size calculation by the sender

Towards high-performance flow-level packet processing on multi-core network processors

Abstract: There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection and flow-based load balancing all require efficient flow-level packet processing. In this paper, we present a design of high-performance flow-level packet processing system based on multi-core network processors. Main contribution of this paper includes: a) A high performance flow classification algorithm optimized for network processors; b) An efficient flow state management scheme leveraging memory hierarchy to support large number of concurrent flows; c) Two hardware-optimized order-preserving strategies that preserve internal and external per-flow packet order. Experimental results show that: a) The proposed flow classification algorithm, AggreCuts, outperforms the well-known HiCuts algorithm in terms of classification rate and memory usage; b) The presented SigHash scheme can manage over 10M concurrent flow states on the Intel IXP2850 NP with extremely low collision rate; c) The performance of internal packet order-preserving scheme using SRAM queue-array is about 70% of that of external packet order-preserving scheme realized by ordered-thread execution.