Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.

Semiconductor circuit device, packet processing method, management system, management method and packet processing method

Abstract: A semiconductor circuit device connected to a communication network, comprising a first receiving buffer where a packet received through the communication network is stored, a first processing circuit for carrying out a first processing according to first partial data contained in a packet stored in the first receiving buffer, a second receiving buffer where second partial data received from the first receiving buffer, different from the first partial data, and contained in the packet stored in the first receiving buffer is stored parallel to at least part of the first processing, and a second processing circuit for carrying out a second processing needing a processing time longer than that of the first processing according to the second partial data stored in the second receiving buffer.

Packet communication device, packet communication system, packet communication module, data processor, and data transfer system

Abstract: A transmit packet generated by a CPU 1 is held in a buffer 100 a ( 100 b ). From among packets received from Ethernet 820 a ( 820 b ), a packet, a destination of which is a communication device 800 , is held in the buffer 100 a ( 100 b ). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820 a or 820 b through a MAC unit 300 a or 300 b . If a transfer judging circuit 200 judges a packet from the Ethernet 820 a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820 b through MAC 300 b . If a usage rate of a transferring FIFO buffer 130 a ( 130 b ) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120 a ( 130 b ) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820 a or 820 b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

Survey of switching techniques in high-speed networks and their performance

Abstract: One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (asynchronous transfer mode). ATM can be characterized by very high speed transmission links and simple, hard-wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks. A number of designs have been proposed for implementing ATM switches. Although many differences exist among the proposals, the vast majority of them are based on self-routeing multistage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routeing capability and suitability for VLSI implementation. Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques have also been proposed to improve the performance of blocking and non-blocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues.

A terabit per second packet switch having assignable multiple packet loss probabilities

Abstract: A physically realizable one terabit or more ATM packet switch that has a large number of input interfaces connected to a single stage switching fabric which is in turn connected to a number of output modules, generally according to the growable packet switch architecture. This ATM packet switch is different from other growable packet switches in that it has a single stage switch fabric controlled by an out-of-band controller, yet it has significantly reduced complexity with respect to comparably sized electronic crossbar switches or their isomorphs. The out-of-band controller has multiple priority levels in order to provide high priority users with a near certainty that their packets will be successfully routed, while delivering an acceptably low packet or cell loss probability to users at the lowest priority level.