Topic
Fast packet switching
About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.
Papers published on a yearly basis
Papers
More filters
Patent•
18 Jun 2004
TL;DR: In this article, a scheduling technique called dynamic packet interleaving is proposed for packet reassembly in large, multiplane, multi-stage switches, where an arbiter in the switch module gives priority to a partial packet (i.e., to a packet that has had at least one cell sent to the queue).
Abstract: Practical packet reassembly in large, multi-plane, multi-stage switches is possible by using a scheduling technique called dynamic packet interleaving. With dynamic packet interleaving scheduling, if more than one packet is contending for the same output link in a switch module, an arbiter in the switch module gives priority to a partial packet (i.e., to a packet that has had at least one cell sent to the queue). The number of reassembly queues required to ensure reassembly is dramatically reduced (e.g., to the number of paths multiplied by the number of scheduling priorities). Deadlock may be avoided by guaranteeing (e.g., reserving) at least one cell space for all partial packets.
38 citations
Patent•
NEC1
TL;DR: In this paper, an optical packet exchange apparatus and an optical switch are used to search for a connection pattern between an input unit devoid of a packet to be transmitted and an output unit without a packet in order to enable fast switch control even in cases where the number of channels is increased or network speed is higher.
Abstract: An optical packet exchange apparatus and an optical switch in which search for a connection pattern between an input unit devoid of a packet to be transmitted and an output unit devoid of a packet to be received is reduced to enable fast switch control even in cases wherein the number of channels of the exchange apparatus is increased or network speed is higher. A plurality of input units, a plurality of output units and an optical switch are provided. Each input unit includes an input buffer unit, a parallel/serial conversion unit, an electrical/optical conversion unit, and a dummy packet insertion unit for sending a dummy packet if there is no packet to be transmitted. Each output unit includes an exchange counterpart contention resolution unit for controlling the exchange counterpart, an optical/electrical conversion unit, a serial/parallel conversion unit, and a packet eliminating unit. The exchange counterpart contention resolution unit controls the packet eliminating unit to eliminate a dummy packet.
38 citations
Patent•
21 Aug 1990TL;DR: In this article, a large N×N packet switch, formed using a plurality of smaller packet switches, is presented, where packets are received at the N inputs to the interconnect fabric, and each packet is routed to one of the inputs of the packet switch associated with the destination user equipment for the packet.
Abstract: This invention is large N×N packet switch, formed using a plurality of smaller packet switches. The invention comprises an N input, L output interconnect fabric (L>N), and a plurality of J×K smaller packet switches (J>K). Each of the J inputs to each packet switch is connected to a separate one of the L outputs of the interconnect fabric, and each of the K outputs from each packet switch is connected to a destination equipment. In operation, packets are received at the N inputs to the interconnect fabric, and each packet is routed to one of the inputs of the packet switch associated with the destination user equipment for the packet. Simultaneous packets, up to J in number, are routed to separate inputs of a particular packet switch for distribution to their respective destinations, while all other simultaneous packets destined for user equipments associated with the same packet switch are lost, the probability of such a loss being acceptably small.
38 citations
27 Nov 1989
TL;DR: A neural network implementation of an input access scheme in a high-speed packet switch for broadband ISDN (integrated services digital network) is presented and the form of the energy function, its optimized parameters, and the connection matrix are given.
Abstract: A neural network implementation of an input access scheme in a high-speed packet switch for broadband ISDN (integrated services digital network) is presented. In this switch, each input maintains a separate queue for each output; thus, in an (n*n) switch there will be n/sup 2/ input queues. Using synchronous operation, at most one packet per input and output will be transferred at every slot. A neural network maximizing the throughput of this switch is determined, and the form of the energy function, its optimized parameters, and the connection matrix are given. Simulations with random inputs have yielded results close to optimal throughput. This neural network can be implemented with the existing technology for medium switching sizes. >
38 citations
Patent•
20 Jun 1985
TL;DR: In this article, the seizure of an outgoing channel is made by scanning and searching a free channel in the bundle, which is the same as the seizure in this paper, but is different in the sense that each packet has inserted in an address field a sequence of addresses respectively assigned to the successive switching network.
Abstract: Multiservice packet telecommunication network in which each packet has inserted in an address field thereof a sequence of addresses respectively assigned to the successive switching network included in a route from a packet sender station to a packet receiver station and defining in these networks groups or bundles of outgoing channels. In each bundle the seizure of an outgoing channel is made by scanning and searching a free channel in the bundle.
38 citations