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Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.


Papers
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Proceedings ArticleDOI
TL;DR: This paper addresses joint transceiver and relay design for a wireless multiple-input multiple-output (MIMO) switching scheme that enables data exchange among multiple users and shows that the optimized MIMO switching scheme based on the proposed algorithms significantly outperforms existing approaches in the literature.
Abstract: This paper addresses joint transceiver and relay design for a wireless multiple-input-multiple-output (MIMO) switching scheme that enables data exchange among multiple users. Here, a multi-antenna relay linearly precodes the received (uplink) signals from multiple users before forwarding the signal in the downlink, where the purpose of precoding is to let each user receive its desired signal with interference from other users suppressed. The problem of optimizing the precoder based on various design criteria is typically non-convex and difficult to solve. The main contribution of this paper is a unified approach to solve the weighted sum mean square error (MSE) minimization and weighted sum rate maximization problems in MIMO switching. Specifically, an iterative algorithm is proposed for jointly optimizing the relay's precoder and the users' receive filters to minimize the weighted sum MSE. It is also shown that the weighted sum rate maximization problem can be reformulated as an iterated weighted sum MSE minimization problem and can therefore be solved similarly to the case of weighted sum MSE minimization. With properly chosen initial values, the proposed iterative algorithms are asymptotically optimal in both high and low signal-to-noise ratio (SNR) regimes for MIMO switching, either with or without self-interference cancellation (a.k.a., physical-layer network coding). Numerical results show that the optimized MIMO switching scheme based on the proposed algorithms significantly outperforms existing approaches in the literature.

32 citations

Book ChapterDOI
J K Annot1, R. A. H. van Twist1
01 Mar 1987
TL;DR: The communication processor presented in this paper was designed such that these phenomena can be proved not to occur and fair usage of the classes and administration of the temporal order of arrival of the packets guarantee that no starvation can occur.
Abstract: Deadlock and starvation are highly undesirable in packet switching networks. The communication processor presented in this paper was designed such that these phenomena can be proved not to occur. Deadlock is avoided using a new method called class climbing; fair usage of the classes and administration of the temporal order of arrival of the packets guarantee that no starvation can occur. The design is generally applicable in all types of networks, independent of topology or size. A planned VLSI implementation is briefly discussed.

32 citations

Patent
Bruce T. Jorgens1, Brian R. Town1
04 Aug 2008
TL;DR: Packet switch test methods include receiving a first packet from a packet switch, receiving a second packet from processing circuitry configured to model expected behavior of the packet switch and comparing the first packet to the second packet, and, based on the comparing, determining whether the packet switches are operating according to the expected behavior as mentioned in this paper.
Abstract: Packet switch test methods include receiving a first packet from a packet switch, receiving a second packet from processing circuitry configured to model expected behavior of the packet switch, comparing the first packet to the second packet, and, based on the comparing, determining whether the packet switch is operating according to the expected behavior. Packet switch modeling methods include identifying functionality of a packet switch to be modeled, creating, in a packet switch model, a plurality of nodes representing physical and/or logical elements of the packet switch, the nodes being configured to process packet data structures and to respectively model different portions of the functionality of the packet switch relative to one another, and, in the packet switch model, connecting the nodes with pathways by which the packet data structures may be forwarded between the nodes.

32 citations

Journal ArticleDOI
TL;DR: This work focuses on tail dropping (TD) and early packet discard (EPD) as selective cell discard schemes which enforce the switches to discard some of the arriving cells instead of relaying them and exactly analyzes the packet loss probability in a system applying these schemes.
Abstract: In transport-layer protocols such as TCP over ATM networks, a packet is discarded when one or more cells of that packet are lost, and the destination node then requires its source to retransmit the corrupted packet. Therefore, once one of the cells constituting a packet is lost, its subsequent cells of the corrupted packet waste network resources. Thus, discarding those cells will enable us to efficiently utilize network resources, and will improve the packet loss probability. We focus on tail dropping (TD) and early packet discard (EPD) as selective cell discard schemes which enforce the switches to discard some of the arriving cells instead of relaying them. We exactly analyze the packet loss probability in a system applying these schemes. Their advantages and limits are then discussed based on numerical results derived through the analysis.

32 citations

Journal ArticleDOI
TL;DR: A novel optical packet switching buffer architecture that is composed of multiple building-block modules, allowing for a large degree of scalability and supporting independent and simultaneous read and write processes without packet rejection or misordering is introduced.
Abstract: We introduce a novel optical packet switching buffer architecture that is composed of multiple building-block modules, allowing for a large degree of scalability. The buffer supports independent and simultaneous read and write processes without packet rejection or misordering and can be considered a fully functional packet buffer. It can easily be programmed to support two prioritization schemes: first-in first-out (FIFO) and last-in first-out (LIFO). Because the system leverages semiconductor optical amplifiers as switching elements, wideband packets can be routed transparently. The operation of the system is discussed with illustrative packet sequences, which are then verified on an actual implementation composed of conventional fiber-optic componentry

32 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
20191
20186
201749
201699
2015159