Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.

A growable packet (ATM) switch architecture: design principles and applications

Abstract: The authors consider the generic problem of designing a large N*N(N>1000) high-performance, broadband packet (or asynchronous transfer mode) switch. They provide ways to construct arbitrarily large switches out of modest-size packet switches, without sacrificing overall delay/throughput performance. They propose and study a growable switch architecture based on three key principles: (a) a generalized knockout principle which exploits the statistical behavior of packet arrivals and thereby reduces the interconnect complexity; (b) output queuing, which yields the best possible delay/throughput performance; and (c) distributed intelligence in routing packets through the interconnect fabric. Other features include the guarantee of a first-in first-out packet sequence, broadcast and multicast capabilities, and compatibility with variable-length packets. In a broadband ISDN (integrated services digital network) example, the authors show a 2048*2048 switch configuration with building blocks of 42*16 packet switch modules and 128*128 interconnect modules. >

Time stamping for a packet switching system

Abstract: A communication method and packet switching system in which packets comprising logical addresses and voice/data information are communicated through the system by packet switching networks (116) which are interconnected by high-speed digital trunks (118, 120) with each of the latter being directedly terminated on both ends by trunk controllers (131, 140). During initial call setup of a particular call, central processors (115) associated with each network in the desired route store the necessary logical to physical address information in the controllers which perform all logical to physical address translations on packets of the call. Each network comprises stages of switching nodes which are responsive to the physical address associated with a packet by a controller to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols. Each packet has a field which is automatically updated by the controllers for accumulating the total time delay incurred by the packet in progressing through the networks. Each processor has the capability of doing fault detection and isolation on the associated network, trunks, and controllers by the transmission of a single test packet. The testing is done solely in response to the test packet and no preconditioning of controllers or networks is necessary.

Packet switching method with time-based routing

Abstract: This invention describes a method for transmitting and forwarding packets over a switching network using time information. The network switches maintain a common time reference, which is obtained either from an external source (such as GPS—Global Positioning System) or is generated and distributed internally. The time intervals are arranged in simple periodicity and complex periodicity (like seconds and minutes of a clock). A data packet that arrives to an input port is switched to an output port based on its order or time position in the time interval in which it arrives at the switch. The time interval duration can be longer than the time duration required for transmitting a data packet, in which case the exact position of a data packet in its forwarding time interval is predetermined. This invention provides congestion-free data packet switching for data packets for which capacity in their corresponding forwarding links and time intervals is reserved in advance. Furthermore, such data packets reach their destination, which can be one or more (i.e., multicast) in predefined time intervals, which guarantees that the delay jitter is smaller than or equal to one time interval

Wavelength routing-based photonic packet buffers and their applications in photonic packet switching systems

Abstract: Photonic packet buffers are essential components in photonic packet switching systems. We present a wavelength routing-based photonic packet buffer based on a state-of-the-art arrayed-waveguide grating (AWG) multiplexer. We show how this new packet buffer can be effectively used in the implementation of photonic packet switching systems. We also propose and examine two different photonic packet switch architectures.

Link-by-link congestion control for packet transmission systems

Abstract: A packet transmission system includes a mechanism for controling congestion (30, FIG. 2) in the transmission system by comparing, at each switching node of the system (52, FIG. 5), the traffic load at that node and the traffic loads at all immediately neighboring switching nodes. Such traffic loads can be measured by node buffer utilization, either discretely or continuously, and loading information exchanged by the use of messages between the switching nodes (42, 54). The packet transmission speed between any two adjacent switching nodes is then adjusted (47, 62) in response to the relative traffic loads so as to reduce the traffic incoming to the more congested node. The transmission speed is never reduced to zero, however, to insure that a mechanism remains in place to relieve congestion at every transmitting switching node.