Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.

Optimal packet size in error-prone channel for IEEE 802.11 distributed coordination function

Abstract: With the popularity of the IEEE 802.11 based wireless network, it has become increasingly important to analyze the performance of the IEEE 802.11 protocol accurately. Throughput and delay are key measures, reflecting the performance of a wireless network. In this paper, we analyze the performance of the IEEE 802.11 distributed coordination function (DCF) in the saturated traffic condition, and consider the effects of packet size, the number of contention nodes, transmission collision probability and channel conditions. Under this analytical framework, we evaluate the impact of error-prone channel on unsuccessful transmission probability and its impact on the performance. A trade-off exists between the desire to reduce the ratio of overhead in the data packet by adopting larger packet size, and the need to reduce the packet error rate in the error-prone environment by using smaller packet length. An optimal packet size can be derived to maximize the throughput of the IEEE 802.11 DCF under various channel conditions and network configurations. To validate our analytical results, we have done extensive simulations, and the simulation results are observed to match very well with the analytical results.

Adaptive error control for packet video in the Internet

Abstract: Anecdotal evidence suggests that the quality of many videoconferences in the Internet is mediocre because of high packet loss rates. This makes it important to design and implement mechanisms that minimize packet loss and its impact in video (and audio) applications. There are two such types of mechanisms. Rate control mechanisms attempt to minimize the amount of packet loss by matching the bandwidth requirements of a video flow to the capacity available in the network. However, they do not prevent packet loss altogether. Error control mechanisms attempt to minimize the visual impact of lost packets at the destinations. We provide motivation for using error control mechanisms based on forward error correction (FEC) and packet reconstruction. We examine a specific mechanism, and evaluate its cost as well as the benefit expected from using it. This mechanism can be augmented to obtain a joint source/channel coding scheme suitable for both the current and the future integrated services Internet.

Switching theory : architectures and performance in broadband ATM networks

Abstract: Broadband Integrated Services Digital Network. Interconnection Networks. Rearrangeable Networks. Non--Blocking Networks. ATM Switch Model. ATM Switching with Minimum--Depth Blocking Networks. ATM Switching with Non--Blocking Single--Queueing Networks. ATM Switching with Non--Blocking Multiple--Queueing Networks. ATM Switching with Arbitrary--Depth Blocking Networks. Appendix. Index.

Fast packet switching system

Abstract: A communication method and packet switching system in which packets comprising logical addresses and voice/data information are communicated through the system by packet switching network (116) which are interconnected by high-speed digital trunks (118) with each of the latter being directly terminated on both ends by trunk collectors (131, 140). During initial call setup of a particular call, central processors (115) associated with each network (116) in the desired route store the necessary logical to physical address information in the controllers which perform all logical to physical address translations on packets of the call. Each network comprises stages of switching nodes which are responsive to the physical address associated with a packet by a controller to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols. Each packet has a field which is automatically updated by the controllers for accumulating the total time delay incurred by the packet in progressing through the networks. Each processor has the capability of doing fault detection and isolation on the associated network, trunks, and controllers by the transmission of a single test packet. The testing is done solely in response to the test packet and no preconditioning of controllers or network is necessary.

Error resilient still image packetization method and packet structure

Abstract: A packetization method and packet structure improve the robustness of a bitstream generated when a still image is decomposed with a wavelet transform. The wavelet coefficients of one “texture unit” are scanned and coded in accordance with a chosen scanning method to produce a bitstream. The bitstreams for an integral number of texture units are assembled into a packet, each of which includes a packet header. Each packet header includes a resynchronization marker to enable a decoder to resynchronize with the bitstream if synchronization is lost, and an index number which absolutely identifies one of the texture units in the packet to enable a decoder to associate following packets with their correct position in the wavelet transform domain. The header information enables a channel error to be localized to a particular packet, preventing the effects of the error from propagating beyond packet boundaries. The invention is applicable to the pending MPEG-4 and JPEG-2000 image compression standards.