Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.

Scheduling and admission control of packet data traffic

Abstract: A method, apparatus and software program is provided for scheduling and admission controlling of real-time data packet traffic. Data packets are admitted or rejected for real-time processing according to throughput capabilities of a packet scheduler. A delivery deadline is determined for each payload data packet at the packet scheduler and packets are sorted into a time-stamp-based queue. Deadline violations are monitored and an adaptation of payload data packets can be triggered on demand in order to enter a stable state.

Implementing distributed packet fair queueing in a scalable switch architecture

Abstract: To support the Internet's growth, there is a need for cost effective switching technologies that can simultaneously provide high capacity switching and advanced QoS. Unfortunately, these two goals are largely believed to be contradictory in nature. To support QoS, sophisticated packet scheduling algorithms, such as fair queueing, are needed to manage queueing points. However, the bulk of current research in packet scheduling algorithms assumes an output buffered switch architecture, whereas most high performance switches are input buffered. While output buffered systems may have the desired QoS, they lack the necessary scalability. Input buffered systems, while scalable, lack the necessary QoS features. We propose the construction of switching systems that are both input and output buffered with the scalability of input buffered switches and the robust QoS of output buffered switches. We call the resulting architecture distributed packet fair queueing (D-PFQ) as it enables physically dispersed line cards to provide a service that closely approximates an output-buffered switch with fair queueing. By equalizing the growth of the virtual time functions across the switch system, most of the PFQ algorithms in the literature can be properly defined for distributed operation. We present our system using a cross bar for the switch core. Buffering techniques are used to enhance the system's latency tolerance, which enables the use of pipelining and variable packet sizes internally. We evaluate the delay and bandwidth sharing properties.

400 Gb/s Programmable Packet Parsing on a Single FPGA

Abstract: Packet parsing is necessary at all points in the modern networking infrastructure, to support packet classification and security functions, as well as for protocol implementation. Increasingly high line rates call for advanced hardware packet processing solutions, while increasing rates of change call for high-level programmability of these solutions. This paper presents an approach for harnessing modern Field Programmable Gate Array (FPGA) devices, which are a natural technology for implementing the necessary high-speed programmable packet processing. The paper introduces PP: a simple high-level language for describing packet parsing algorithms in an implementation-independent manner. It demonstrates that this language can be compiled to give high-speed FPGA-based packet parsers that can be integrated alongside other packet processing components to build network nodes. Compilation involves generating virtual processing architectures tailored to specific packet parsing requirements. Scalability of these architectures allows parsing at line rates from 1 to 400 Gb/s as required in different network contexts. Run-time programmability of these architectures allows dynamic updating of parsing algorithms during operation in the field. Implementation results show that programmable packet parsing of 600 million small packets per second can be supported on a single Xilinx Virtex-7 FPGA device handling a 400 Gb/s line rate.

Congestion-free transmission of real-time traffic in packet networks

Abstract: The process of packet clustering in a network with well-regulated input traffic is studied. Based on this study, a strategy for congestion-free communication in packet networks is proposed. The strategy provides guaranteed services per connection with no packet loss and an end-to-end delay which is a constant plus a small bounded jitter term. Therefore, it provides an attractive solution for the transmission of real-time traffic in packet networks. The strategy is composed of an admission policy imposed per connection at the source node and a particular queuing scheme, called stop-and-go queuing, practiced at the switching nodes. The admission policy requires the packet stream of each connection to possess a certain smoothness property upon arrival to the network, while the queuing scheme eliminates the process of packet clustering and thereby preserves the smoothness property as packets travel inside the network. Implementation of the stop-and-go queuing is simple, with little processing overhead and minor hardware modifications to the conventional FIFO (first in, first out) queuing structure. >

Rapidly switching all-optical packet routing system with optical-label swapping incorporating tunable wavelength conversion and a uniform-loss cyclic frequency AWGR

Abstract: This letter discusses an experimental demonstration of a rapidly switching all-optical packet routing system with optical-label switching and all-optical label-swapping capabilities. The optical routing system optically extracts the subcarrier optical-label content, compares it against the forwarding table, makes packet forwarding and label-swapping decisions, and forward the packet to the desired output with a newly updated subcarrier optical label. The packet switching fabric included a combination of rapidly tunable wavelength conversion and a uniform-loss cyclic frequency 8/spl times/8 arrayed waveguide grating router. The packet routing system achieved 600-ps switching time and 250-ns forwarding decision time. Accumulated packet bit-error-rate measurements confirm the successful error-free packet routing with all-optical label-swapping.