Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.

Method and apparatus for packet transmission with header compression

Abstract: A sender converts a non-compressed packet, which is to be transmitted, into a full-header packet including a full header or a header-compressed packet including a compressed header, and sends the converted packet to a receiver The receiver receives the packet transmitted from the sender, and converts the received packet into a decompressed packet In cases the full-header packet or header-compressed packet is lost between the sender and receiver, the receiver keeps header-compressed packers received during an interval from the packet loss to the next earliest reception of a full-header packet, and decompresses the compressed headers of the kept header-compressed packets on the basis of contents of the full header of the full-header packet

Method and apparatus for robust packet distribution among hierarchical managed switching elements

Abstract: For a network that includes several managed edge switching elements and several managed non-edge switching elements that are for implementing a logical switching element, some embodiments provide a method of distributing packet processing across the several managed non-edge switching elements. The method receives a packet for processing through the logical switching element. Based on a determination that the packet needs to be processed by a managed non-edge switching element, the method determines a particular managed non-edge switching element of the several managed non-edge switching elements to forward the packet. The method forwards the packet to the particular managed non-edge switching element for the particular managed non-edge switching element to process the packet.

External memory engine selectable pipeline architecture

Abstract: External memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The route switch packet architecture includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

Multimedia-aware quality-of-service and error correction provisioning

Abstract: Methods and apparatus for associating each data packet in a media stream with logic corresponding to a particular quality-of-service (QoS) and/or error correction requirement. In an exemplary embodiment, each packet in the media stream is assigned a frame tag which designates a particular quality-of-service and/or error correction scheme for the corresponding packet. At least a portion of each packet is encoded according to the packet's designated quality-of-service as indicated by the frame tag. A receiver accesses the frame tags from within the transmitted media stream in order to determine the appropriate means for processing or decoding the encoded portion of each packet. In this manner, each packet within the media stream can have its own quality-of-service and/or error correction requirements and processing, thereby enhancing link efficiency and better enforcing QoS policy across the system.

Method of transmitting data in a wireless communication system

Abstract: A method of generating a data block to be transmitted from a protocol layer to a receiving side in a wireless communication system, the protocol layer having a header compression function, comprises generating at least one of a control packet which includes control information and a compressed packet generated by header compression for an upper layer data block, and generating a first lower layer data block which includes type indication information and the control packet, if the control packet is generated, the type indication information indicating a type of control information included in the generated control packet.