Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.

Packet radio communication system protocol

Abstract: A method and apparatus for transmitting data in a packet radio communication system having data sources, destinations and intermediate repeaters. According to a packet protocol, a repeat count in the protocol is decremented each time a packet is retransmitted, until the repeat count reaches zero, at which time the packet is discarded. According to another packet protocol, a sequence index is used to prevent duplicate packets from being received by requiring that the sequence number fall within a sequence number window at each device, which is incremented each time a packet is received. The sequence number is also used to cause the retransmission of packets which are lost, at which time the sequence number windows in the devices which are affected are reset to allow transmission of the lost packet.

Combined pipelined classification and address search method and apparatus for switching environments

Abstract: A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented. The method performed by the apparatus includes: determining a packet frame type of the packet received; selectively extracting packet header field values specific to a packet frame type, the extracted packet header field value including packet addressing information; ascribing to the packet a preliminary action to be performed in respect of the packet; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into one of a plurality of packet flows; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet in accordance with the switch response. Advantages are derived from: pipelined processing of packets which enables short-cutting the rest of the processing for improper packets; a flexible frame type determination which is fast for well know frame types yet flexible in support of new frame types delaying obsolescence of a particular implementation; an early determination of a processing action which is successively refined by subsequent stages; a combined Layer-2 and Layer-3 network addressing search engine operating on short bit length indexed Layer-2 and Layer-3 network addresses reducing network address table storage requirements, requiring a reduced data transfer bandwidth for network address table access, a large external hashed primary network address table, and a small internal secondary network address table; an early determination of a switch response; and packet-classification-based switch response and packet header modification.

Dual port memory buffers and a time slot scheduler for an atm space division switching system

Abstract: An asynchronous transfer mode switching network system relays packets stored in packet buffer units to output ports designated by the packets, and a time slot scheduling unit assigns time slots to the packets stored in the packet buffer units upon arrival at the packet buffer units for preventing the packets from collision in a space division switching unit, wherein each of the packet buffer units sequentially writes new packets into respective memory locations but randomly reads out the new packets in the time slots assigned by the time slot scheduling unit so that the throughput of the space division switching unit is improved.

Packet processing device

Abstract: A packet processing device in which a receiving buffer free space notifying portion notifies a free space of a receiving buffer, an accumulation condition determining portion determines a size of a big packet based on the free space, and a reassembly buffer processor reassembles a plurality of receiving packets into a single big packet to be transmitted to the receiving buffer. A backward packet inclusive information reading circuit for detecting the free space based on information within a backward packet from the upper layer may be used as the receiving buffer free space notifying portion. Also, an application layer may be used as the upper layer so that the big packet is transmitted not through a buffer of a transport layer but directly to the receiving buffer.

Method and apparatus for transmission of high priority traffic on low speed communication links

Abstract: In a packet switched communications system an incoming real-time packet is imbedded after the next block of data of the non-real-time packet being transmitted. This object is accomplished by transmitting each packet along with at least a 1-byte trailer which is used to indicate the packet type, whether the current block of non real time data is preempted or whether the current block of non real time data is resumed.