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Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.


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Patent
Suk-jin Yun1, Junwhan Kim1
03 Mar 2005
TL;DR: In this paper, the authors propose a method and apparatus to dynamically control data traffic, such as multimedia streams, needing a guaranteed Quality of Service (QoS) and normal data traffic according to a variable communication environment.
Abstract: A method and apparatus dynamically control data traffic, such as multimedia streams, needing a guaranteed Quality of Service (QoS) and normal data traffic, according to a variable communication environment. The method of dynamically controlling traffic in a wireless station includes reading header information of a packet received from an upper layer and determining a type of the packet, setting a priority according to the type of the packet, adjusting a size of a variable buffer by performing appropriate dynamic buffering according to the type of the packet, enqueuing the packet in a fixed buffer if the priority is high and enqueuing the packet in the variable buffer if the priority is low, and transmitting the packet enqueued in the fixed buffer to a destination station prior to the packet enqueued in the variable buffer.

63 citations

Patent
22 May 2001
TL;DR: In this article, the authors proposed a centralized control and signaling interworking function (CS-IWF) device that performs call control functions and adminstrative functions and is adapted to interface narrowband and broadband signaling for call processing and control within the ATM switching network.
Abstract: An Asynchronous Transfer Mode (ATM)-based distributed network switching system includes an ATM switching network (26) that dynamically sets up individual switched virtual connections. The system also includes multiple access interworking function (A-IWF) devices each operating as a gateway that enables customer premises devices to directly interface into the distributed ATM switching fabric. The system further includes a centralized control and signaling interworking function (CS-IWF) device that performs call control functions and adminstrative functions and is adapted to interface narrowband and broadband signaling for call processing and control within the ATM switching network (26). The CS-IWF device (30) may be a server farm.

63 citations

01 Jan 1998
TL;DR: In this article, the authors examine the correlation between packet delay and packet loss experienced by a continuous-media traffic source on the Internet and study the extent to which one performance measure can be used to predict the future behavior of the other.
Abstract: In this paper we examine the correlation between packet delay and packet loss experienced by a continuous-media traffic source on the Internet. Our goal is to study the extent to which one performance measure can be used to predict of the future behavior of the other (e.g., whether observed increasing delay is a good predictor of future loss) so that an adaptive continuous media application might take {\it anticipatory\/} action based on observed performance. We ran numerous hour-long experiments in which continuous media traffic was sent from a source to a destination. We measured the per-packet delay and packet loss and then analyzed our measurements off-line. Our results provide a quantitative study of the extent to which such correlation exists. Interestingly, we observe periodic phenomena in the correlation that we had initially not expected. We discuss our results, speculate as to the reason for the observed behaviors, and discuss their implications for adaptive continuous media applications.

63 citations

Patent
04 Jun 1992
TL;DR: In this paper, a credit manager circuit determines whether a stored packet complies with predetermined traffic parameters such as average arrival rate and maximum burst rate, based on a packet's arrival time and its virtual channel identifier (VCI).
Abstract: A method and system are provided for controlling user traffic to a fast packet switching system using the leaky bucket scheme. Each of the packets (53 byte length cell) originates at a source of packets and has a virtual channel identifier (VCI). The method includes the step of receiving the packets, each of the packets having associated therewith an arrival time. The packets are stored at an addressable location in a first memory. The first memory having a plurality of addressable locations. In a second memory, there are stored addresses corresponding to the addressable locations in the first memory in which a packet is not yet stored. The addresses stored in the second memory are utilized in the step of storing the received packets. A credit manager circuit determines whether a stored packet complies with predetermined traffic parameters such as average arrival rate and maximum burst rate. This determination is based on a packet's arrival time and its VCI to obtain a validated packet. The credit manager circuit retrieves the validated packet from the first memory and the retrieved packet is then transmitted to the packet switching system.

63 citations

Patent
23 Jun 1986
TL;DR: In this paper, the authors proposed a packet switching protocol in which self-routing packets are communicated among stages of switching nodes via inter-stage links, where data of the packets is transmitted in one direction (210) and packet clocking signals are transmitted in the other direction (211).
Abstract: A communication method and packet switching network (101) in which self-routing packets are communicated among stages of switching nodes via inter-stage links (204-215) whereon data of the packets is transmitted in one direction (210) and the packet clocking signals are transmitted in the other direction (211). Upon having the capability to accept a packet from one of the interstage links, a switch node transmits the packet clock signals to the upstream stage connect to that link indicating the present capacity to accept a packet. Furthermore, each switch node after receiving the end of a packet from an upstream stage waits for a predefined duration of time before commencing the transmission of the packet clocking signals. That delay allows the transmitting switch node i the upstream stage to determine that the link and downstream node are functioning correctly since continued transmission of the packet clock signals indicates that the packet had not been received or that downstream node had incorrectly responded to receipt of the packet. If a malfunction is detected, an error indication is transmitted to the computer controlling the switching network.

63 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
20191
20186
201749
201699
2015159