Fast packet switching

About: Fast packet switching is a research topic. Over the lifetime, 5641 publications have been published within this topic receiving 111603 citations.

High‐Speed Downlink Packet Access

Abstract: This chapter presents High-speed Downlink Packet Access (HSDPA) for WCDMA—the key new feature included in Release 5 specifications. The HSDPA concept has been designed to increase packet data throughput by means of fast physical layer (L1) retransmission and transmission combining as well as fast link adaptation controlled by the Node B (Base Transceiver Station (BTS)). This chapter is organised as follows: First, HSDPA key aspects are presented and a comparison to Release’99 downlink packet access possibilities is made. Next, the impact of HSDPA on the terminal uplink (user equipment (UE)) capability classes is summarised and an HSDPA performance analysis is presented, including a comparison to Release’99 packet data capabilities. The chapter is concluded with a short discussion of evolution possibilities of HSDPA.

Frame-based matching algorithms for input-queued switches

Abstract: We focus on input-buffered packet switches, which are traditionally controlled slot-by-slot with heuristic approximations (such as iSLIP) of maximum weight or size matching algorithms. We consider instead a frame-based control strategy, in which f slots are grouped in a frame, and contentions are solved only at frame boundaries. A number of frame-based heuristics is described, and simulation is used to show that our approach provides performance advantages over a slot-by-slot control in a number of traffic scenarios.

Integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and for outputting both ATM and packet data

Abstract: An integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and outputting packets containing information from both the packet and ATM input data. The integrated ATM/packet segmentation-and-reassembly engine is also configured for receiving packets containing information destined for transmission as ATM cells and information destined for transmission as packets, perform the segregation function and segmentation function on the information destined for transmission as ATM cells in order to output both ATM cells and packets. Architecture includes the ability to output both ATM cells and packets on a single optical fiber.

Communication node and packet transfer method

Abstract: A communication node which can reliably transfer a packet with a payload including data having error resistance in radio environments is disclosed. A packet to be transmitted is divided into segments to form a plurality of packet segments. From among a plurality of error correction schemes that have been prepared in advance, the scheme to be employed is selected for each of the packet segments in accordance with predetermined criteria, and the selected error correction scheme is applied to each packet segment. Subsequently, the processed packet segment is transmitted to the network. Packet segments are received from the network. From among a plurality of error correction schemes prepared in advance, the scheme to be employed is selected for each of the received packet segments based on predetermined information contained in each received packet segment, and the selected error correction scheme is applied to the received packet segment. An original packet is formed from the plurality of processed packet segments.