Showing papers on "Fault coverage published in 1971"
TL;DR: Two procedures are presented for generating fault detection test sequences for large sequential circuits using an adaptive random procedure and an algorithmic path-sensitizing procedure that employs a three-valued logic system.
Abstract: Two procedures are presented for generating fault detection test sequences for large sequential circuits. In the adaptive random procedure one can achieve a tradeoff between test generation time, length, and percent of circuit tested. An algorithmic path-sensitizing procedure is also presented. Both procedures employ a three-valued logic system. Some experimental results are given.
75 citations
TL;DR: Every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network con be obtained and this model greatly simplifies fault analysis and test generation.
Abstract: A network model colled the normal NAND model is introduced for the study of fault diagnosis in combinational logic circuits. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network con be obtained. The use of this model greatly simplifies fault analysis and test generation.
73 citations
TL;DR: It is shown that, under certain conditions, internal fan-out may be present without adversely affecting the detection of multiple faults and this suggests design techniques which lead to readily diagnosable networks.
Abstract: This paper considers the design of diagnosable combinational networks. The diagnosability criterion used here requires that the single fault detection test set for the network also detects all multiple faults. Several recent studies in the area of multiple fault diagnosis are reviewed and the results which are pertinent to this investigation are summarized. It is shown that, under certain conditions, internal fan-out may be present without adversely affecting the detection of multiple faults. These results suggest design techniques which lead to readily diagnosable networks.
32 citations
TL;DR: Techniques for deriving the minimum length tests are developed for irredundant combinational circuits that contain single faults due to the expansion of the Boolean difference function to form two analytical expressions.
Abstract: Techniques for deriving the minimum length tests are developed for irredundant combinational circuits that contain single faults The development is based on the Boolean difference function The Boolean difference function is expanded to form two analytical expressions that can be used to calculate the tests for any stuck-at-zero and stuck-at-one fault within combinational circuits
14 citations
TL;DR: In this paper, an algorithm is presented for designing minimum-expected-cost test trees for detecting and isolating single faults in a system, where each component is assumed to have an a priori probability of failure and each test is associated with a fixed cost.
Abstract: An algorithm is presented for designing minimum-expected-cost test trees for detecting and isolating single faults in a system. A test is specified by the subset of components that must be good for the test to pass, and with each test is associated a fixed cost. Each component is assumed to have an a priori probability of failure. The test tree specifies an adaptive testing procedure that detects a failure and isolates the faulty component while minimizing the expected cost of testing.
10 citations