scispace - formally typeset
Search or ask a question

Showing papers on "Fault coverage published in 1974"


Journal ArticleDOI
TL;DR: In this article, a branch-and-bound algorithm is developed for selecting an optimal (or near-optimal) set of q test points in fanout-free networks, and some difficulties associated with test point placement in general networks are pointed out.
Abstract: The problem of selecting test points to reduce the number of tests for fault detection in combinational logic networks is examined. A method is presented for labeling the lines of a network. Procedures are described for obtaining a minimal labeling, i.e., one corresponding to a minimal set of tests, for fanout-free circuits and for a restricted class of circuits with fanout. Using these procedures, a branch-and-bound algorithm is developed for selecting an optimal (or near-optimal) set of q test points in fanout-free networks. Some difficulties associated with test point placement in general networks are pointed out. It is shown that the labeling approach is also applicable to the problem of selecting and placing control logic.

114 citations


Journal ArticleDOI
TL;DR: This paper attempts to outline procedures and identify problem areas so that test generation is more of a science rather than a hit and miss process, and so that the correctness of results need not always be verified via simulation or physical fault injection.
Abstract: Test sequences constructed by most test generation procedures often create time dependent results when applied to a circuit. These dependencies often invalidate the test. The main cause for this situation is that the test generation procedures and circuit models employed do not take into account many aspects of delay associated with a circuit. In this paper we present modeling techniques to be used by conventional test generation procedures to alleviate some of these problems. These models include the cases of equal, unequal and ambiguous delay values. Both inertial and transport delays are considered. Both static and dynamic output behavior is studied, though we restrict inputs to fundamental mode operation. Finally, a new type of fault, caUed a delay fault, is introduced, and a model developed so that a test to detect this class of fault can be generated via conventional test generation techniques. In summary, this paper attempts to outline procedures and identify problem areas so that test generation is more of a science rather than a hit and miss process, and so that the correctness of results need not always be verified via simulation or physical fault injection.

38 citations


Journal ArticleDOI
TL;DR: The problem of how to determine minimal sets of tests for single and multiple faults in irredundant combinational circuits is dealt with and it is shown that the "Equivalent Sum of Products" form of the given network contains all the information necessary to derive a min; mal test set.
Abstract: The problem of how to determine minimal sets of tests for single and multiple faults in irredundant combinational circuits is dealt with It is shown that the "Equivalent Sum of Products" form of the given network contains all the information necessary to derive a min; mal test set A simple procedure which generates a minimal test set Ts for single faults is described Fault masking is then studied and it is shown how to find the multiple faults undetected by Ts Finally a method which derives a nearly minimal multiple fault test set Tm where Ts [mi][/mi] Tm is given

19 citations


Journal ArticleDOI
TL;DR: A general design technique for achieving single fault-tolerant asynchronous sequential circuits is described and real time fault detection is easily achieved and it is immediately known when single fault tolerant capability is exceeded.
Abstract: A general design technique for achieving single fault-tolerant asynchronous sequential circuits is described. The design procedures apply over a large range of fault conditions and are extremely easy to use. Generally, less than three times the logic required for a single copy is needed to achieve single fault tolerance. In addition to fault tolerance, real time fault detection is easily achieved and it is immediately known when single fault tolerant capability is exceeded.

14 citations


Proceedings ArticleDOI
01 Jan 1974
TL;DR: The techniques to be described in this paper are generally applicable to any time domain, parallel fault, digital logic simulation system and the particular implementation was done on the CC-TEGAS3 system and quoted results are from this system.
Abstract: The techniques to be described in this paper are generally applicable to any time domain, parallel fault, digital logic simulation system. The particular implementation was done on the CC-TEGAS3 system and quoted results are from this system.The first technique to be considered provides accuracy of fault simulation when using assignable nominal delays for different element types. The second technique provides for handling fault induced activity in a network, in such a way as to considerably reduce the amount of simulation time required.

13 citations


Proceedings ArticleDOI
01 Jan 1974
TL;DR: A series of programs was developed, over the years, to completely automate the test cycle—using logic description files as input, the final output for test generation is a test deck compiled in the language of card test equipment and, in the case of test-verification, lists of detected and undetected failures.
Abstract: The widespread use of large scale and medium scale integrated circuits, coupled with the trend towards larger boards, made manual generation of test patterns very expensive, somewhat ineffective, and rather difficult to update for design changes. The advent of MOS LSI's with extremely large gate density made manual test-verification, the process of finding failures detected by a given test pattern, an impossibility. Therefore, a series of programs was developed, over the years, to completely automate the test cycle—using logic description files as input, the final output for test generation is a test deck compiled in the language of card test equipment and, in the case of test-verification, lists of detected and undetected failures. All this is accomplished within the global constraint of complete (nearly 100%) coverage and prevailing test floor practices.

7 citations


Journal ArticleDOI
TL;DR: The LSI quality measure can be related to component yield and is based on the stuck fault testing coverage, the physical circuit design layout, and the rate of faults occurring on elemental circuit geometries.
Abstract: Large-scale integration components are subjected to testing based on stuck fault modeling. Stuck fault testing often does not provide patterns for all possible stuck conditions that can exist in a circuit. Because of the incompleteness of test coverage, a new quality measure is needed-one that is not based on sample inspection. Such an LSI quality measure is described in this paper. The LSI quality measure can be related to component yield and is based on the stuck fault testing coverage, the physical circuit design layout, and the rate of faults occurring on elemental circuit geometries. The concept of the LSI quality measure is illustrated in this paper by an example. Starting from a block diagram and an assumed stuck fault coverage, some stuck faults are assumed to remain untested. For these untested faults, the elemental circuit geometries in a corresponding FET circuit layout are determined, and the quality measure calculated. Common sense rules are offered for optimizing the quality and lowering its cost impact on higher levels of assembly.

6 citations


Journal ArticleDOI
TL;DR: Bosson and Hong1 have developed an effective procedure for multiple fault detection and claim that their procedure gives near-minimal results, but this is not necessarily the case.
Abstract: Bosson and Hong1 have developed an effective procedure for multiple fault detection. However, their claim that their procedure gives near-minimal results is not necessarily the case.

1 citations


Journal ArticleDOI
P. Goel1, D.P. Siewiorek
TL;DR: Some comments on a recent contribution on multiple fault detection using test sets for single fault detection are presented and a counter example that shows some defects in generalizing from a tree to an arbitrary network are included.
Abstract: Some comments on a recent contribution on multiple fault detection using test sets for single fault detection are presented. A counter example that shows some defects in generalizing from a tree to an arbitrary network are also included.

1 citations



Journal ArticleDOI
01 Aug 1974
TL;DR: In this paper, the phase-angle criterion of the block-average type of comparator is a function of the primary system quantities and is therefore continuously variable between well defined limits around the characteristic boundary.
Abstract: Contemporary methods of providing specially shaped relay characteristics, i.e. other than the familiar circular and straight-line types, are assessed, particularly from the point of view of relay performance and complexity. A new method of shaping is established in which the phase-angle criterion of the block-average type of comparator is a function of the primary system quantities and is therefore continuously variable between well defined limits around the characteristic boundary. This method of shaping affords precise design, which is confirmed by comparisons of experimental and theoretical results. The applications described are limited to providing a characteristic with optimum fault coverage but which has increased immunity from extreme balanced system conditions such as heavy loads and power swings. Further applications, to provide characteristics that will accommodate high fault resistances, will be considered in a later paper.